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CS302 Final Term Solved MCQs Mega File by Sonu Ilyas

Digital Logic Design PDF 1.3 MBUpdated 23 Oct 2026
Final term past paper CS302 Final Term Solved MCQs Mega File by Sonu Ilyas PDF 1.3 MB
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Final term past paper
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CS302 Digital Logic Design
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23 Oct 2026
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CS302 Digital Logic Design Solved MCQs Final Term (AIO)

Q1. A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register. (1 marks)

  1. 1
  2. 2
  3. 4
  4. 8 (Page 356)

Correct answer: 8 (Page 356)

Q2. (1 marks)

  1. State variable, current state
  2. Current state, flip-flop output
  3. Current state and external input (Page 318)
  4. Input and clock signal applied

Correct answer: Current state and external input (Page 318)

Q3. The divide-by-60 counter in digital clock is implemented by using two cascading counters: (1 marks)

  1. Mod-6, Mod-10 (Page 299)
  2. Mod-50, Mod-10
  3. Mod-10, Mod-50
  4. Mod-50, Mod-6

Correct answer: Mod-6, Mod-10 (Page 299)

Q4. (1 marks)

  1. True (Page 221)
  2. False

Correct answer: True (Page 221)

Q5. (1 marks)

  1. Set-up time
  2. Hold time (Page 242)
  3. Pulse Interval time
  4. Pulse Stability time (PST)

Correct answer: Hold time (Page 242)

Q6. (1 marks)

  1. ENP, ENT (Page 285)
  2. ENI, ENC
  3. ENP, ENC
  4. ENT, ENI

Correct answer: ENP, ENT (Page 285)

Q7. ____________ is said to occur when multiple internal variables change due to change in one input variable (1 marks)

  1. Clock Skew
  2. Race condition (Page 267)
  3. Hold delay
  4. Hold and Wait

Correct answer: Race condition (Page 267)

Q8. (1 marks)

  1. Asynchronous, synchronous (Page 369)
  2. Synchronous, asynchronous
  3. Preset input (PRE), Clear input (CLR)
  4. Clear input (CLR), Preset input (PRE)

Correct answer: Asynchronous, synchronous (Page 369)

Q9. (1 marks)

  1. Mod-3 counter
  2. Mod-5 counter
  3. Mod-8 counter
  4. Mod-10 counter (Page 274)

Correct answer: Mod-10 counter (Page 274)

Q10. (1 marks)

  1. It is set to logic low
  2. It is set to logic high (Page 356)
  3. Remains in previous state
  4. State of transmission line is not used to start transmission

Correct answer: It is set to logic high (Page 356)

Q11. (1 marks)

  1. 2
  2. 4 (Page 394)
  3. 8
  4. 16

Correct answer: 4 (Page 394)

Q12. (1 marks)

  1. 1
  2. 0
  3. A

Correct answer: A

Q13. (1 marks)

  1. 1110
  2. 1100
  3. 1000
  4. 0000 (Page 34)

Correct answer: 0000 (Page 34)

Q14. (1 marks)

  1. Vout / Vin = - Rf / Ri (Page 446)
  2. Vout / Rf = - Vin / Ri
  3. Rf / Vin = - Ri / Vout
  4. Rf / Vin = Ri / Vout

Correct answer: Vout / Vin = - Rf / Ri (Page 446)

Q15. (1 marks)

  1. Look Up Table (Page 439)
  2. Local User Terminal
  3. Least Upper Time Period
  4. None of given options

Correct answer: Look Up Table (Page 439)

Q16. (1 marks)

  1. AND, NAND, XOR
  2. OR, AND, NAND
  3. NOT, NOR, XOR
  4. NOT, OR, AND (Page 40)

Correct answer: NOT, OR, AND (Page 40)

Q17. (1 marks)

  1. The organization of memory
  2. The structure of memory
  3. The size of decoding unit
  4. The size of the address bus of the microprocessor (Page 430)

Correct answer: The size of the address bus of the microprocessor (Page 430)

Q18. (1 marks)

  1. FIFO memory
  2. LIFO memory (Page 429)
  3. Flash Memory
  4. Bust Flash Memory

Correct answer: LIFO memory (Page 429)

Q19. (1 marks)

  1. 213
  2. 123
  3. 127
  4. 345

Correct answer: 127

Q20. ___________ is one of the examples of synchronous inputs. (1 marks)

  1. J-K input (Page 235)
  2. EN input
  3. Preset input (PRE)
  4. Clear Input (CLR)

Correct answer: J-K input (Page 235)

Q21. __________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. (1 marks)

  1. Race condition
  2. Clock Skew (Page 226)
  3. Ripple Effect
  4. None of given options

Correct answer: Clock Skew (Page 226)

Q22. Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be ___________ (1 marks)

  1. 0000
  2. 1101 (not sure)
  3. 1011
  4. 1111

Correct answer: 1101 (not sure)

Q23. In a state diagram, the transition from a current state to the next state is determined by (1 marks)

  1. Current state and the inputs (Page 332)
  2. Current state and outputs

Correct answer: Current state and the inputs (Page 332)

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