- Type
- Final term past paper
- Course
- CS302 Digital Logic Design
- Size
- PDF 489 KB
- Updated
- 23 Oct 2026
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Text from pages 1, 2, 3 of 51. Download the file for all 51 pages.
PSMD01(IEMS)
Spring 2011
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.
Correct answer: 8 (Page 356)
Q2. (1 marks)
Q4. (1 marks)
____________ is said to occur when multiple internal variables change due to change in one input variable
Correct answer: Race condition (Page 267)
The _____________ input overrides the ________ input
Correct answer: Asynchronous, synchronous (Page 369)
A decade counter is __________.
Correct answer: Mod-10 counter (Page 274)
In asynchronous transmission when the transmission line is idle, _________
Correct answer: It is set to logic high (Page 356)
A Nibble consists of _____ bits
Correct answer: 4 (Page 394)
The output of this circuit is always ________.
Excess-8 code assigns _______ to “-8”
Correct answer: 0000 (Page 34)
The voltage gain of the Inverting Amplifier is given by the relation ________
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