CS302 Grand Quiz

Digital Logic Design (CS302) · Multiple Choice Questions (MCQs) · Objective Questions

1. In case of cascading Integrated Circuit counters, the enable inputs and RCO of the Integrated Circuit counters allow cascading of multiple counters together.
2. True
3. False
4. Two types of memories namely the first in-first out (FIFO) memory and last in first out (LIFO) are implemented using ________.
5. Shift Registers
6. Circular Buffers
7. Ring Buffers
8. Reduce Registers
9. `
10. The Synchronous SRAM also has a Burst feature which allows the Synchronous SRAM to read or write up to ________ location(s) using a single address.
11. One
12. Two
13. Three
14. Four

4. When the transmission line is idle in an asynchronous transmission

1. It is set to logic low
2. It is set to logic high
3. It remains in previous state
4. State of transmission line is not used to start transmission

5. A multiplexer with a register circuit converts

1. Serial data to parallel
2. Parallel data to serial
3. Serial data to serial
4. Parallel data to parallel
5. ________ is used when the output is connected back to the input of the PAL or if the output pin is used as an input only.
6. Combinational Input/Output
7. Combinational Output
8. Combinational Input
9. Programmable polarity

7. The terminal count of a 4-bit binary counter in the UP mode is

1. 1100
2. 0011
3. 1111
4. 0000
5. A SOP expression can be implemented by an ________ combination of gates.
6. OR-XOR
7. AND-NAND
8. AND-OR
9. XOR-NOR
10. The n flip-flops store ________ states.
11. 1
12. 2^n
13. 0
14. 2^(n+1)
15. The AND Gate performs a logical ________ function.
16. Addition
17. Substraction
18. Multiplication
19. Division
20. The S-R latch has two inputs, therefore ________ different combinations of inputs can be applied to control the operation of the S-R latch.
21. two
22. four
23. eight
24. sixteen
25. Implementation of Latch is required almost ________ transistor.
26. Two
27. Four
28. Six
29. Eight
30. For a Standard SOP expression, a ________ is placed in the cell corresponding to the product term (Minterm) present in the expression.
31. 0
32. 1
33. x (don't care condition)
34. Any of given option depending on SOP term
35. Demorgan's two theorems prove the equivalency of the NAND and ________ gates and the NOR and ________ gates respectively.
36. Negative-OR, Negative-AND
37. Negative-AND, Positive-OR
38. Positive-OR, Negative-AND
39. Positive-OR, Positive-AND
40. The normal data inputs to a flip-flop (D, S and R, J and K, T) are referred to as ________ inputs.
41. Sequential
42. Asynchronous
43. Synchronous
44. Combinational
45. The Test Vector definition defines the test vectors for all the three counter inputs and ________ counter output/outputs.
46. One
47. Two
48. Three
49. Four

17. Select the mode of programming in which GAL16V8 can be programmed:

1. Simple Mode
2. Complex Mode
3. Registered Mode
4. All of the given
5. If the voltage drop across the active load is 0 volts due to absence of current the comparator output is a ________.
6. 0
7. 1
8. The ROM used by a computer is relatively ________ as it stores few byres of code used to Boot the Computer system on power up.
9. Small
10. Large
11. Heavy
12. High
13. In NAND based S-R latch, output of each ________ gate is connected to the input of the other ________ gate.
14. NOR, NAND
15. NAND, NOR 3. NOR, NOR 4. NAND, NAND
16. The outputs of SR latches in elevator state machine are feed back to the ________ gate array for connection to the D-flipflops.