CS302 Semester Quiz 4 Jan 2026

Quiz 1 - CS302 (Q1/10)

Question:

With a 100 KHz clock frequency, eight bits can be serially entered into a shift register in

A. 10 micro seconds B. 8 micro seconds

C. 80 micro seconds

D. 80 mili seconds Copied: 1/8/2026, 10:11:10 PM

Quiz 2 - CS302 (Q2/10)

Question:

When an eight bit serial in/out shift register is used for a 24 micro seconds time delay, the clock frequency must be

A. 41.67 KHz B. 125 KHz C. 8 MHz

D. 333 KHz

Copied: 1/8/2026, 10:12:02 PM

Quiz 3 - CS302 (Q3/10)

Question:

According to Moore circuit, the output of synchronous sequential circuit depend/s on ______ of flip flop.

A. Next State

B. External Inputs

C. Present State

D. Previous State Copied: 1/8/2026, 10:12:52 PM

Quiz 4 - CS302 (Q4/10)

Question:

Once the state diagram is drawn for any sequential circuit the next step is to draw

A. Transiation table

B. Next-state table

C. Logic expression D. Karnaugh map Copied: 1/8/2026, 10:13:49 PM

Quiz 5 - CS302 (Q5/10)

Question:

Which mechanism allocate the binary values to the states in order to reduce the cost of the combinational circuits?

1. State Evaluation
2. State Minimization
3. State Assignment
4. State Reduction

Correct answer: State Assignment

Copied: 1/8/2026, 10:14:11 PM

Quiz 6 - CS302 (Q6/10)

Question:

The normal data inputs to a flip-flop (D, S and R, J and K, T) are referred to as ________ inputs.

A. Synchronous

B. Asynchronous C. Sequential D. Combinational Copied: 1/8/2026, 10:14:44 PM

Quiz 7 - CS302 (Q7/10)

Question:

If data is brought into the J terminal and its complement to the K terminal, a J-K flip-flop operates as a(n) ________.

A. S-C flip-flop

B. D flip-flop

C. S-R flip-flop D. N flip-flop Copied: 1/8/2026, 10:15:13 PM

Quiz 8 - CS302 (Q8/10)

Question:

Karnaugh map is used in designing

A. a clock