CS302 Solved Quiz 1 Set 2 by VUBuddy

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CS302 QUIZ 1 SOLVED

Q1. The terminal count of a 4-bit binary counter in the UP mode is

1. 1100
2. 0011
3. 1111
4. 0000

Correct answer: 1111

Q2. For a down counter that counts from (111 to 000). If current state is “101” the next state will be .

1. 111
2. 110
3. 010
4. None of given options

Correct answer: 110

3. The n flip-flops store states.

1. 1
2. 2^n
3. 0

Correct answer: 2^n

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d) 2^(n+1)

Q4. An Asynchronous Down-counter is implemented (using J-K flip-flop) by connecting

1. Q output of all flip-flops to clock input of next flip-flops
2. Q’ output of all flip-flops to clock input of next flip-flops
3. Q output of all flip-flops to J input of next flip-flops
4. Q’ output of all flip-flops to K input of next flip-flops

Correct answer: Q output of all flip-flops to clock input of next flip-flops

Q5. In case of cascading Integrated Circuit counters, the enable inputs and RCO of the Integrated Circuit counters allow cascading of multiple counters together.

1. True
2. False

Correct answer: True

Q6. A decade counter can be implemented by truncating the counting sequence of a MOD-20 counter.

1. True
2. False

Correct answer: False

7. The 74HC163 is a 4-bit Synchronous Counter, it has data output pins.

1. 2
2. 4

Correct answer: 4

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c) 6 d) 8

8. Counters as the name indicates are not triggered simultaneously

a) Asynchronous

b) Synchronous c) Positive-Edge triggered d) Negative-Edge triggered

Q9. Divide-by-32 counter can be achieved by using

1. Flip-Flop and DIV 10
2. Flip-Flop and DIV 16
3. Flip-Flop and DIV 32
4. DIV 16 and DIV 32

Correct answer: Flip-Flop and DIV 16

10. The input overrides the input

1. Asynchronous, synchronous
2. Synchronous, asynchronous
3. Preset input (PRE), Clear input (CLR)
4. Clear input (CLR), Preset input (PRE)

Correct answer: Asynchronous, synchronous