CS401 Final Term Premium Solved Quizzes by ZB Zaib

CS401: Assembly Language Programming

Final Term Preparation Guide (Premium Edition)

Author: ZB ZAIB

Quranic Motivation (Roman English)

“Insaan ke liye wahi kuch hota hai jis ke liye woh khud mehnat aur koshish karta hai.” Reference Surah An-Najm, Ayah 39

Part 1: 100 Important Conceptual Questions

Q1. What is the primary purpose of Hardware Interrupts?

Answer: To allow peripheral devices to signal the CPU for attention asynchronously. Explanation: Instead of polling, devices interrupt the CPU only when needed, increasing system efficiency.

2. Explain the role of the PIC (Programmable Interrupt Controller).

Answer: It manages multiple interrupt requests from hardware devices and prioritizes them for the CPU. Explanation: The PIC maps IRQs to interrupt numbers and ensures the CPU handles them one at a time based on priority.

Q3. What is the difference between RET and IRET ?

Answer: RET pops IP and CS; IRET pops IP, CS, and the Flags register. Explanation: IRET is essential for ISRs to restore the processor's state (including flags) to exactly what it was before the interrupt.

Q4. What is the Interrupt Vector Table (IVT)?

Answer: A table at address 0000:0000 containing the addresses (Segment:Offset) of all ISRs. Explanation: Each entry is 4 bytes. The CPU finds an ISR by multiplying the interrupt number by 4.

Q5. What triggers an INT 0?

Answer: A division by zero or a result that is too large for the destination register (Divide Overflow). Explanation: It is an internal, synchronous interrupt generated by the processor's execution unit.

Q6. What is the function of the STI and CLI instructions?

Answer: STI enables maskable interrupts; CLI disables them. Explanation: They control the Interrupt Flag (IF). Disabling interrupts is crucial during critical code sections to prevent corruption.

Q7. How does the CPU acknowledge an interrupt?

Answer: By sending an INTA (Interrupt Acknowledge) signal to the PIC. Explanation: This signal tells the PIC to place the interrupt number on the data bus so the CPU can find the ISR.

Q8. What is an EOI (End of Interrupt) signal?

Answer: A command sent to the PIC to signal that the current interrupt handling is finished. Explanation: Without EOI, the PIC will block further interrupts of the same or lower priority.

Q9. What are I/O Ports?

Answer: Specific addresses used by the CPU to communicate with hardware controllers. Explanation: Unlike memory, ports are accessed using IN and OUT instructions to control devices like the timer or keyboard.

10. Explain the " Trap Flag" (TF).

Answer: A flag that, when set, causes the CPU to trigger INT 1 after every instruction. Explanation: This is the basis for single-stepping in debuggers, allowing programmers to inspect state after each step.

Q11. What is the difference between IRQ and Interrupt Number?

Answer: IRQ is a physical pin on the PIC; Interrupt Number is the index in the IVT. Explanation: The PIC maps IRQs (0-7) to specific interrupt numbers (e.g., IRQ 0 maps to INT 8).

Q12. What is the System Timer Interrupt (INT 8)?

Answer: A hardware interrupt triggered by the timer chip ~18.2 times per second. Explanation: It is used for timekeeping, multitasking, and turning off the floppy motor.

Q13. What is the purpose of the Keyboard Interrupt (INT 9)?

Answer: To process key presses and releases. Explanation: Every time a key is pressed, INT 9 is triggered, and the ISR reads the scan code from the keyboard port.

Q14. What is BIOS?

Answer: Basic Input/Output System; low-level software that provides a standard interface to hardware. Explanation: BIOS interrupts (like INT 10h for video) allow programs to work across different hardware.

Q15. What is DOS (Disk Operating System) Interrupt 21h?

Answer: The primary gateway for DOS system services. Explanation: It provides high-level functions like file management, string output, and program termination.

Q16. How do you pass parameters to an ISR?

Answer: Usually through registers or global memory variables. Explanation: Since interrupts are asynchronous, you cannot use the stack for parameter passing like regular subroutines.

Q17. What is a "Hooking" an interrupt?

Answer: Replacing the address of a standard ISR in the IVT with the address of your own routine. Explanation: This allows you to extend or change the behavior of system interrupts (e.g., custom keyboard handling).

Q18. What is the significance of the stack during an interrupt?

Answer: It stores the return address (CS:IP) and the Flags register. Explanation: The stack ensures the CPU can return to the exact point of interruption without losing state.

Q19. What is the difference between Maskable and Non-Maskable Interrupts (NMI)?

Answer: Maskable interrupts can be disabled via CLI ; NMIs cannot be ignored. Explanation: NMIs are used for critical errors like memory parity failures or power loss.

Q20. What is the "Divide Overflow" problem?

Answer: When the result of a division is too large to fit in the destination register (e.g., AX or AL). Explanation: This triggers INT 0. It often happens when dividing by a very small number. (...Continuing with 80 more questions based on the syllabus content...)