CS501 Final Term Solved MCQs with References by Arslan

Solved MCQ(S) · From FinalTerm Papers · BY Arslan · Jan 14, 2018 · V-U

Updated.

Final-Term Papers Solved MCQs with Reference

Q1. What is the instruction length of the FALCON-A processor?

•  8 bits

 16 bits PG # 91

•  32 bits
•  64 bits

Q2. What is the working of Processor Status Word (PSW)?

 To hold the current status of the processor. PG # 25

•  To hold the address of the current process
•  To hold the instruction that the computer is currently processing
•  To hold the address of the next instruction in memory that is to be executed

Q3. What functionality is performed by the instruction “str R8, 34” of SRC?

•  it will load the register R8 with the contents of the memory location M [PC+34]
•  It will load the register R8 with the relative address itself (PC+34).
•  It will store the register R8 contents to the memory location M [PC+34] PG # 48
•  No operation

4. FALCON-A processor bus has 16 lines or is 16-bits wide while that of SRC is __________ wide.

•  8-bits
•  24-bits

 32-bits PG # 157

•  64-bits

5.op<4..0>:= IR<15..11>:

The above RTL instruction presents the __________ of the FALCON-A Instructions.

 operation code field PG # 105

•  target register field
•  operand or address index
•  second operand

Q6. Which one of the following register holds the address of the next instruction to be executed?

•  Accumulator
•  Address Mask
•  Instruction Register

 Program Counter PG # 151

Q7. Which one of the following register holds the instruction that is being executed?

•  Accumulator
•  Address Mask

 Instruction Register PG # 152

•  Program Counter

8. ________ operation is required to change the processor‟s state to a known, defined value.

•  Change

 Reset PG # 194

•  Update
•  Halt

9. Type B format of SRC uses -----------instructions

•  Two

 Three PG # 47

•  Four
•  Five

10. ________ control signal enable the CON circuitry to operate, and instruct it to check for the appropriate condition (whether it is branch if zero, or branch if not equal to zero, etc.)

•  ECON
•  BCON

 LCON PG # 184

•  VCON

Q11. In which one of the following addressing modes, data is the part of the instruction itself, and so there is no need of address calculation?

•  Direct Addressing Mode

 Immediate addressing mode PG # 40

•  Indirect Addressing Mode
•  Register (Direct) Addressing Mode

12. ___________ is a technique in which some of the CPU‟s address lines forming an input to the address decoder are ignored.

 Partial decoding PG # 255

•  Full encoding
•  Partial multiplexing
•  Half encoding