CS609 Final Term Notes by Saeed

DMA Controller

DMA is a device which can acquire complete control of the buses and hence can be used to transfer data directly from port to memory or vice versa. Transferring data like this can prove faster because a transfer will consume 2 bus cycles if it is performed using the processor. So in this approach the processor is bypasses and its cycles are stolen and are used by the DMA controller.

Direct Memory Access (DMA)

The latch B of the DMA interface is used to hold the higher 4 or 8 bits of the 20 or 24 bit absolute address respectively. The lower 16bits are loaded in the base address register and the number of bytes to be loaded are placed in the count register. The DMA requests to acquire buses through the HOLD signal, it receives a HLDA (Hold Acknowledge ) signal if no higher priority signal is available. On acknowledgment the DMA acquires control of the buses and can issue signals for read and write operations to memory and I/O ports simultaneously. The DREQ signals are used by various devices to request a DMA operation. And if the DMA controller is successful in acquiring the bus it sends back the DACK signal to signify that the request is being serviced. For the request to be serviced properly the DMA channel must the programmed accurately before the request.

A single DMA can transfer 8bit operands to and from memory in a single a bus cycle. If 16bit values are to be transmitted then two DMA controllers are required and should be Cascaded

DMA Programming Model

• DMA has 4 – Channels
• Each Channel can be programmed to transfer a

block of maximum size of 64k.

• For each Channel there is a

• Base Register

• Count Register

• Higher Address Nibble/Byte is placed in Latch B.
• The Mode register is conveyed which Channel is

to be programmed and for what purpose i.e. Read Cycle, Write Cycle, Memory to memory transfer.

• A request to DMA is made to start it’s transfer.

DMA Modes · • Block Transfer · • Single Transfer · • Demand Transfer

In block transfer mode the DMA is programmed to transfer a block and does not pause or halt until the whole block is transferred irrespective of the requests received meanwhile. In Single transfer mode the DMA transfers a single byte on each request and updates the counter registers on each transfer and the registers need not be programmed again. On the next request the DMA will again transfer a single byte beginning from the location it last ended. Demand transfer is same as block transfer, only difference is that the DREQ signal remains active throughout the transfer and as soon as the signal deactivates the transfer stops and on reactivation of the DREQ signal the transfer may start from the point it left.

Terminal count if reached signifies that the whole of the block as requested through some DMA channel has been transferred.

This is the command register. It is used to program various common parameters of transfer for all the channels. This register can be used to simulate a DMA request through software (in case of memory to memory transfer). The lower 2 bits contains the channel number to be requested and the bit # 2 is set to indicate a request.

This register can be used to mask/unmask requests from a device for a certain DMA channel. The lower 2 bits contains the channel number and the bit #2 is set if the channel is to be masked.

This register can also be used to mask the DMA channels. It contains a single bit for each channel. The corresponding bit is set to mask the requests for that channel.

This register can be used to set the mode on each. The slide shows the detail of the values and bits which should be placed in the register in order to program a required mode.