CS302 Final Term Past Papers by VUBuddy

CS302- Digital Logic Design · LATEST SOLVED MCQS FROM FINAL TERM PAPERS · 19-12-2011 Latest Mcqs

PSMD01(IEMS)

Spring 2011

A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.

1. 1
2. 2
3. 4
4. 8 (Page 356)

Correct answer: 8 (Page 356)

Q2. In a sequential circuit the next state is determined by ________ and _______ (1 marks)

1. State variable, current state
2. Current state, flip-flop output
3. Current state and external input (Page 318)
4. Input and clock signal applied

Correct answer: Current state and external input (Page 318)

The divide-by-60 counter in digital clock is implemented by using two cascading counters:

1. Mod-6, Mod-10 (Page 299)
2. Mod-50, Mod-10
3. Mod-10, Mod-50
4. Mod-50, Mod-6

Correct answer: Mod-6, Mod-10 (Page 299)

Q4. In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained. (1 marks)

1. True (Page 221)
2. False

Correct answer: True (Page 221)

The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.

1. Set-up time
2. Hold time (Page 242)
3. Pulse Interval time
4. Pulse Stability time (PST)

Correct answer: Hold time (Page 242)

74HC163 has two enable input pins which are _______ and _________

1. ENP, ENT (Page 285)
2. ENI, ENC
3. ENP, ENC
4. ENT, ENI

Correct answer: ENP, ENT (Page 285)

____________ is said to occur when multiple internal variables change due to change in one input variable

1. Clock Skew
2. Race condition (Page 267)
3. Hold delay
4. Hold and Wait

Correct answer: Race condition (Page 267)

The _____________ input overrides the ________ input

1. Asynchronous, synchronous (Page 369)
2. Synchronous, asynchronous
3. Preset input (PRE), Clear input (CLR)
4. Clear input (CLR), Preset input (PRE)

Correct answer: Asynchronous, synchronous (Page 369)

A decade counter is __________.

1. Mod-3 counter
2. Mod-5 counter
3. Mod-8 counter
4. Mod-10 counter (Page 274)

Correct answer: Mod-10 counter (Page 274)

In asynchronous transmission when the transmission line is idle, _________

1. It is set to logic low
2. It is set to logic high (Page 356)
3. Remains in previous state
4. State of transmission line is not used to start transmission

Correct answer: It is set to logic high (Page 356)

A Nibble consists of _____ bits

1. 2
2. 4 (Page 394)
3. 8
4. 16

Correct answer: 4 (Page 394)

The output of this circuit is always ________.

1. 1
2. 0

Excess-8 code assigns _______ to “-8”

1. 1110
2. 1100
3. 1000
4. 0000 (Page 34)

Correct answer: 0000 (Page 34)

The voltage gain of the Inverting Amplifier is given by the relation ________

1. Vout / Vin = - Rf / Ri (Page 446)
2. Vout / Rf = - Vin / Ri
3. Rf / Vin = - Ri / Vout
4. Rf / Vin = Ri / Vout
5. Look Up Table (Page 439)
6. Local User Terminal
7. Least Upper Time Period
8. None of given options