CS302 Final Term MCQs 2026 by VUBuddy

Q1. A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is

1. 64 mW
2. 25 mW
3. 1024 mW
4. 10 mW

Correct answer: 25 mW

Q2. The 74HC163 is a 4-bit Synchronous Counter.it has..............data output pins

1. 8
2. 2
3. 6
4. 4

Correct answer: 4

Q3. In gated SR latch, what is the value of the output if EN=1, S=0 and R=0?

1. 1
2. Invalid
3. 0
4. Qt

Correct answer: Qt

Q4. In 8-input multiplexer, the two outputs are connected through a/an _____ gate.

1. OR
2. AND
3. NOT
4. NOR

Correct answer: OR

Q5. In 8-input multiplexer, when ___ is set to 0, the first multiplexer is selected allowing its inputs 1C0, 1C1, 1C2 and 1C3 to be selected.

1. D
2. A
3. B
4. C

Correct answer: A

Q6. 2-Input, 8-bit Multiplexer, by setting the S input to logic ____ the __ inputs of both the multiplexers are selected.

1. Low, C
2. High, B
3. Low, B
4. Low, C

Correct answer: Low, B

Q7. A synchronous decade counter will have _______ flip-flops

1. 10
2. 3
3. 4
4. 7

Correct answer: 4

Q8. The OLMC can be configured to provide a feedback input signal to the AND gate array input. There are ___________ possibilities.

1. two
2. three
3. four
4. five

Correct answer: four

Q9. The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.

1. Pulse Stability time (PST)
2. Set-up time
3. Pulse Interval time
4. Hold time

Correct answer: Set-up time

Q10. A mono-stable device only has a single stable state

1. False
2. True

Correct answer: True

Q1. The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________

1. It does not show transition on change in pulse
2. Doesn’t have an invalid state
3. Sets to clear when both J = 0 and K = 0
4. It does not accept asynchronous inputs

Correct answer: Doesn’t have an invalid state

Q2. RCO stands for __________

1. Ripple Counter Output
2. Ripple Clock Output
3. Reconfiguration Counter Output
4. Reconfiguration Clock Output

Correct answer: Ripple Clock Output

Q3. PLDs have In-System Programming (ISP) capability that allows the _________ to be programmed after they have been installed on a circuit board.

1. PLAs
2. EPROM
3. PALs
4. PLDs

Correct answer: PLDs

Q4. A NOR based S-R latch is implemented using _______ gates instead of _________ gates.

1. NOR,NAND
2. XOR,NAND
3. NOR,XOR
4. OR,XOR

Correct answer: NOR,NAND

Q5. ABEL is an acronym for

1. Advanced Boolean Expression Language
2. Advanced Broadband Enabled Longitude
3. Advanced Boolean Equation Language
4. None of the given options

Correct answer: Advanced Boolean Equation Language

Q6. An Asynchronous Down-counter is implemented (Using J-K flip-flop) by connecting ________

1. Q’ output of all flip-flops to K input of next flip-flops
2. Q’ output of all flip-flops to clock input of next flip-flops
3. Q output of all flip-flops to J input of next flip-flops
4. Q output of all flip-flops to clock input of next flip-flops

Correct answer: Q’ output of all flip-flops to clock input of next flip-flops