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CS302 Midterm MCQs 21 Files Merged by Jamil Hussain

Digital Logic Design PDF 28.7 MBUpdated 23 Oct 2026
Midterm past paper CS302 Midterm MCQs 21 Files Merged by Jamil Hussain PDF 28.7 MB
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Midterm past paper
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CS302 Digital Logic Design
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PDF 28.7 MB
Updated
23 Oct 2026
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Text from pages 2, 3, 4 of 1441. Download the file for all 1441 pages.

Spring 2010

Q1. A SOP expression is equal to 1 ______________ (1 marks)

  1. All the variables in domain of expression are present
  2. At least one variable in domain of expression is present.
  3. When one or more product terms in the expression are equal to 0.
  4. When one or more product terms in the expression are equal to 1. (Page 86)

Correct answer: When one or more product terms in the expression are equal to 1. (Page 86)

Q2. The output A < B is set to 1 when the input combinations is __________ (1 marks)

  1. A=10, B=01
  2. A=11, B=01
  3. A=01, B=01
  4. A=01, B=10 (Page 109)

Correct answer: A=01, B=10 (Page 109)

Q3. Two 2-bit comparator circuits can be connected to form single 4-bit comparator (1 marks)

  1. True (Page 154)
  2. False

Correct answer: True (Page 154)

Q4. High level Noise Margins (VNH) of CMOS 5 volt series circuits is _____________ (1 marks)

  1. 0.3 V
  2. 0.5 V
  3. 0.9 V (Page 65)
  4. 3.3 V

Correct answer: 0.9 V (Page 65)

Q5. If we multiply “723” and “34” by representing them in floating point notation i.e. by first, converting them in floating point representation and then multiplying them, the value of mantissa of result will be ________ (1 marks)

  1. 24.582 (But not sure)
  2. 2.4582
  3. 24582
  4. 0.24582

Correct answer: 24.582 (But not sure)

Q6. The output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the symbol‟+‟ here represents OR Gate. (1 marks)

  1. Undefined
  2. One
  3. Zero
  4. 10 (binary)

Correct answer: One

Q7. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be (1 marks)

  1. SET (page 220)
  2. RESET
  3. Clear
  4. Invalid

Correct answer: SET (page 220)

Q8. 3.3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series. (1 marks)

  1. Low switching speeds, high power dissipation
  2. Fast switching speeds, high power dissipation
  3. Fast switching speeds, very low power dissipation (page61)
  4. Low switching speeds, very low power dissipation

Correct answer: Fast switching speeds, very low power dissipation (page61)

Q9. (1 marks)

  1. 86 (According to Formula)
  2. 87
  3. 88
  4. 89

Correct answer: 86 (According to Formula)

Q10. The _______ Encoder is used as a keypad encoder. (1 marks)

  1. 2-to-8 encoder
  2. 4-to-16 encoder
  3. BCD-to-Decimal
  4. Decimal-to-BCD Priority (Page 166)

Correct answer: Decimal-to-BCD Priority (Page 166)

Q11. How many data select lines are required for selecting eight inputs? (1 marks)

  1. 1
  2. 2
  3. 4

Q12. NOT (1 marks)

Gate level AND Gate level OR Gate level

the diagram above shows the general implementation of ________ form

  1. boolean
  2. arbitrary
  3. POS
  4. SOP

Correct answer: SOP

Q13. (1 marks)

  1. 4 (Page 217)
  2. 8
  3. 12
  4. 16

Correct answer: 4 (Page 217)

Q14. Demultiplexer has (1 marks)

  1. Single input and single outputs.
  2. Multiple inputs and multiple outputs.
  3. Single input and multiple outputs. (Page 178)
  4. Multiple inputs and single output.

Correct answer: Single input and multiple outputs. (Page 178)

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CS302 Digital Logic Design All CS302 handouts, past papers, quizzes and MCQs in one place. Open course page

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