- Type
- Midterm past paper
- Course
- CS302 Digital Logic Design
- Size
- PDF 241 KB
- Updated
- 23 Oct 2026
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CS302Digital Logic Design
Q1. A SOP expression is equal to 1 ______________ (1 marks)
All the variables in domain of expression are present At least one variable in domain of expression is present. When one o r more product terms in the expression are equal to 0. When one or more product terms in the expression are equal to 1. (Page 86)
Q2. The output A < B is set to 1 when the input combinations is __________ A (1 marks)
=10, B=01 A=11, B=01 A=01, B=01 A=01, B=10 (Page 109)
Q3. Two 2-bit comparator circuits can be connected to form single 4-bit comparator (1 marks)
True (Page 154) False
Q4. High level Noise Margins (VNH) of CMOS 5 volt series circuits is (1 marks)
- 3 V
- 5 V
- 9 V (Page 65)
- 3 V
Q5. If we multiply “723” and “34” by representing them in floating point notation i.e. by first, converting them in floating point representation and then multiplying them, the value of mantissa of result will be ________ (1 marks)
- 582 (But not sure)
- 4582
24582
- 24582
Q6. The output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the symbol‟+‟ here represents OR Gate. (1 marks)
Undefined One Zero 10 (binary)
Q7. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be________. (1 marks)
SET (page 220) RESET Clear Invalid
Q8. 3.3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series. (1 marks)
Low switching speeds, high power dissipation Fast switching speeds, high power dissipation Fast switching speeds, very low power dissipation (page61) Low switching speeds, very low power dissipation
Q9. The binary value “1010110” is equivalent to decimal __________ 86 (According to Formula) (1 marks)
Q10. The _______ Encoder is used as a keypad encoder. (1 marks)
-to-8 encoder -to-16 encoder BCD -to-Decimal Decimal -to-BCD Priority (Page 166)
Q11. How many data select lines are required for selecting eight inputs? (1 marks)
Q12. the diagram above shows the general implementation of ________ form boolean (1 marks)
arbitrary POS SOP
Q13. The Quad Multiplexer has _____ outputs (1 marks)
4 (Page 217)
Q14. Please choose one Demultiplexer has (1 marks)
Single input and single outputs. Multiple inputs and multiple outputs. Single input and multiple outputs. (Page 178) Multiple inputs and single output.
Q15. The expression _________ is an example of Commutative Law for Multiplication. (1 marks)
AB+C = A+BC A(B+C) = B(A+C) AB=BA (Page 72) A+B=B+A
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