CS302 Quiz 2 by Junaid

1. The transition table is very similar to the table a. Truth b. State c. Transition d. None of the given option
2. Two Signals and provide the timing inputs to the state machine a. NSSR and EWSR b. LTIME and STIME page 374 c. PTIME and QTIME d. NSGrn and NSYel
3. Memories are implemented in bit data unit sizes a. 1 , 2 and 6 b. 2 , 3 and 6 c. 1 , 4 and 8 d. 4 , 5 and 8
4. In distributed mode, for a 1024 X 1024 DRAM memory and a refresh cycle of 8msec, each of the 1024 rows has to be refreshed in when distributed refresh is used a. 4.8 microsec b. 5.9 micorsec c. 7.8 micorsec d. 5.5 microsec
5. The EPROM uses array with an isolated gate structure a. NMOSFET page 411 b. MOSFETK c. UVMOSFT d. None of the given options

Q6. The 64-cell array organized as 8 X 8 cell array is considered

1. As an 64 byte memory
2. As a 16 byte memory
3. As an 8 byte memory
4. As an 4 byte memory
5. The test vector definition defines the test vector for all the three counter inputs and counter output/outputs

1. One
2. Two
3. Three
4. Four

Q8. In memory write cycle, the time for which the WE signal remains active is known as the

1. Write address setup
2. Write pulse width
3. Write delay width
4. Write Data Time

Q9. If the voltage drop across the active load is 0 volts due to absence of current the comparator output is a

1. 0
2. 1

Q10. As data values are written or read from RAM stack, the stack pointer register increments or decrements its contents always pointing to the stack

1. Bottom
2. Top
3. Down
4. Vertex

Q11. A 4-bit binary up/down counter in in the binary state of zero. The next state in the DOWN mode is?

1. 0001
2. 1000
3. 1110
4. 1111
5. Flash memory operation are classified into different operations

1. Two
2. Three
3. Four
4. Five
5. Implementation of latch is required almost transistor?

1. Two
2. Four
3. Six
4. Eight
5. In elevator circuit, the floor display circuit is a combinational circuit which uses the and inputs two determine the floor number and the function of the display arrow.

1. CONSTATE, FB
2. OPEN, DIR
3. MOTION, DIR
4. MOTION, FB

Q15. The bit capacity of memory that has 1024 addresses and can store 8 bit at each address is

1. 8
2. 1024
3. 4096

Q16. When the transmission line is idle in an asynchronous transmission

1. It is set to logic low
2. It remains in previous state
3. State of transmission line is not used to start transmission

Q17. Which of the following is a volatile memory?

1. PROM
2. DRAM

page 400(capacitor based ROM, need extra circuit to retain the memory) c. EPROM d. EEPROM

Q18. Which signal must remain valid in memory write cycle after data is applied at the data input lines and must remain valid for a minimum time duration tWD ?

1. `CS
2. `WE
3. W
4. OE
5. The ROM used by computer is relatively very as it stores few bytes of code used to boot the computer system on power up

1. Small
2. Large
3. Heavy
4. High

Q20. In DRAM read cycle R/W signal is activated to read data which is made available on the Data line

1. D(IN)
2. D(OUT)
3. D(AB)
4. 8192

page 388(memory capacity) 1024*8=8192

b. It set to logic high