- Type
- Quiz
- Course
- CS302 Digital Logic Design
- Size
- PDF 1.8 MB
- Updated
- 23 Oct 2026
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Four
1. In case of cascading Integrated Circuit counters, the enable inputs and RCO of the Integrated
Circuit counters allow cascading of multiple counters together.
1. True
2. False
2.
Two types of memories namely the first in-first out (FIFO) memory and last in first out
(LIFO) are implemented using
1. Shift Registers
2. Circular Buffers
3. Ring Buffers
4. Reduce Registers
3.
The Synchronous SRAM also has a Burst feature which allows the Synchronous SRAM to
single address.
1. One
2. Two
3. Three
4.
4.
When the transmission line is idle in an asynchronous transmission
1. It is set to logic low
3. It remains in previous state
4. State of transmission line is not used to start transmission
5.
A multiplexer with a register circuit converts
1. Serial data to parallel
3. Serial data to serial
4. Parallel data to parallel
6.
is used when the output is connected back to the input of the PAL or if the
output pin is used as an input only.
1. Combinational Input/Output
- It is set to logic high
- Parallel data to serial
12. Implementation of Latch is required almost
transistor.
1.
Two
2.
Four
3.
Six
4. Eight
corresponding to the product term (Minterm) present in the expression.
- 0
- 1
3. x (don't care condition)
4. Any of given option depending on SOP term Three Synchronous
14. Demorgan's two theorems prove the equivalency of the NAND and
gates and the NOR and
gates respectively.
1. Negative-OR, Negative-AND
2. Negative-AND, Positive-OR
3. Positive-OR, Negative-AND
4. Positive-OR, Positive-AND
15. The normal data inputs to a flip-flop (D, S and R, J and K, T) are referred to as
inputs.
1. Sequential
2. Asynchronous 3.
- Combinational
- The Test Vector definition defines the test vectors for all the three counter inputs and
counter output/outputs.
1. One
2. Two
3.
- Four
17. Select the mode of programming in which GAL16V8 can be programmed:
1. Simple Mode
2. Complex Mode
3. Registered Mode
- If the voltage drop across the active load is 0 volts due to absence of current the comparator
output is a
- 0
19. The ROM used by a computer is relatively
as it stores few byres
of code used to Boot the Computer system on power up.
2. Large
3. Heavy
4. High
20. In NAND based S-R latch, output of each
gate is connected to the input of the other
gate.
1. NOR, NAND
2. NAND, NOR 3. NOR, NOR
4. NAND, NAND
21. The outputs of SR latches in elevator state machine are feed back to the
gate array for
connection to the D-flipflops.
- All of the given
- 1
- Small
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