CS302P Final Term Solved Quiz 6 Spring 2025 by Introvert
- Type
- Final term past paper
- Course
- CS302P Digital Logic Design (Practical)
- Size
- PDF 418 KB
- Updated
- 23 Oct 2026
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CS302p quiz 6 solution by introvert
Q1. There are ______ cells in a 4-variable K-map
Correct answer: 16
Q2. How many select lines would be required for an 8x1 multiplexer?
Correct answer: 1
Q3. A full adder circuit takes ______________ bit(s) as input and returns ____________ bit(s) as output
Correct answer: 2, 1
Q4. When implementing a half adder by using gates, which of the following gates is used to return carry bit as an output?
Correct answer: OR
Q5. In order to build an XOR gate using NAND gates only, ______________ gate(s) are required
Correct answer: 2
Q1. How many select lines would be required for an 8x1 multiplexer?
Correct answer: 8
Q2. It should be kept in mind that don’t care terms should be used along with the terms that are present in
Correct answer: Expressions
Q3. When implementing a half adder by using gates, which of the following gates is used to return carry bit as an output?
Correct answer: XOR
Q4. Which of the following gates is used for parity generation for a binary data string?
Correct answer: OR
Q5. In order to build an XOR gate using NAND gates only, ______________ gate(s) are required
Correct answer: 1
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