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CS302P Final Term Solved Quiz 6 Spring 2025 by Introvert

Digital Logic Design (Practical) PDF 418 KBUpdated 23 Oct 2026
Final term past paper CS302P Final Term Solved Quiz 6 Spring 2025 by Introvert PDF 418 KB
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Final term past paper
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CS302P Digital Logic Design (Practical)
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PDF 418 KB
Updated
23 Oct 2026
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CS302p quiz 6 solution by introvert

Q1. There are ______ cells in a 4-variable K-map

  1. 20
  2. 16
  3. 24
  4. 8

Correct answer: 16

Q2. How many select lines would be required for an 8x1 multiplexer?

  1. 2
  2. 8
  3. 1
  4. 3

Correct answer: 1

Q3. A full adder circuit takes ______________ bit(s) as input and returns ____________ bit(s) as output

  1. 2, 2
  2. 2, 1
  3. 3, 2
  4. 3, 1

Correct answer: 2, 1

Q4. When implementing a half adder by using gates, which of the following gates is used to return carry bit as an output?

  1. OR
  2. XOR
  3. AND
  4. NAND

Correct answer: OR

Q5. In order to build an XOR gate using NAND gates only, ______________ gate(s) are required

  1. 1
  2. 4
  3. 2
  4. 3

Correct answer: 2

Q1. How many select lines would be required for an 8x1 multiplexer?

  1. 2
  2. 8
  3. 3
  4. 1

Correct answer: 8

Q2. It should be kept in mind that don’t care terms should be used along with the terms that are present in

  1. Minterms
  2. K-Map
  3. Expressions
  4. Latches

Correct answer: Expressions

Q3. When implementing a half adder by using gates, which of the following gates is used to return carry bit as an output?

  1. NAND
  2. OR
  3. XOR
  4. AND

Correct answer: XOR

Q4. Which of the following gates is used for parity generation for a binary data string?

  1. XOR
  2. OR
  3. NOR
  4. AND

Correct answer: OR

Q5. In order to build an XOR gate using NAND gates only, ______________ gate(s) are required

  1. 2
  2. 1
  3. 3
  4. 4

Correct answer: 1

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