CS302P Solved Sample Paper 2025 by Qalb-e-Momin

Sample Paper

FINALTERM EXAMINATION

Fall 2022 CS302P – Digital Logic Design (Practical)

Time: 90 min Marks: 40

MCQ Part

Q1. Generally, for checking the result in a single bit, we use _________ indicator.

1. Logic Converter
2. Logic Tester
3. Probe
4. 7-sagment Display

Correct answer: Probe

Q2. We can simplify a logic circuit using ____________ device in Electronic Workbench.

1. Truth Table
2. Boolean Algebra
3. Circuit Minimizer
4. Logic Converter

Correct answer: Logic Converter

Q3. If Z = (A+B'+C)' then Z will be logic high only if ___________.

1. A = 1, B = 1, C = 1
2. A = 0, B = 0, C = 0
3. A = 0, B = 1, C = 0
4. A = 0, B = 0, C = 1

Correct answer: A = 0, B = 1, C = 0

Q4. A logic circuit having N inputs, can have ____________ different input combinations.

1. N x N
2. 2 x N
3. N+2
4. 2^N

Correct answer: 2^N

Q5. In a 4-bit odd counter, if the current state is 0001 then the next state will be

1. 0010
2. 0000
3. 0011
4. 1100

Correct answer: 0011

Q6. The 4-bit grey code for the binary 1001 will be _______________.

1. 1100
2. 0011
3. 1111
4. 1101

Correct answer: 1101

Q7. What will be boolean expression for the function F(A, B, C) = Π(0, 1, 3, 7)

1. (A+B+C)(A+B+C’)(A+B’+C’)(A’+B’+C’)
2. (A+B’+C)(A+B+C’)(A’+B’+C)(A+B+C)
3. (A’+B’+C)(A’+B+C’)(A’+B+C)(A’+B’+C’)
4. (A’+B+C)(A+B’+C)(A+B+C’)(A’+B’+C’)

Correct answer: (A+B+C)(A+B+C’)(A+B’+C’)(A’+B’+C’)

Q8. Which of the following is the correct maxterm ID for the term x+y’+z?

1. M2
2. M5
3. m2
4. m5

Correct answer: M2

Q9. Which of the following gates is used to get the sum output of the full adder circuit?

1. AND
2. OR
3. NOR
4. XOR

Correct answer: XOR

Q10. To build an XOR gate using basic gates only, _____________ gates can be used?

1. 4 NAND
2. 2 NAND
3. 2 NOR
4. 4 NOR

Correct answer: 4 NAND

Q11. Which of the following is correct expression for carry output in a half-adder circuit?

1. A XOR B
2. A NOR B
3. A AND B
4. A NAND B

Correct answer: A AND B

Q12. Consider the given circuit, what value will be displayed on 7-segment display when the simulation is activated?

1. 3
2. 12
3. d
4. 6

Correct answer: d

Q13. When using full adders to build a 4-bit parallel subtractor circuit, the carry input of which of the full adders is always set to 1?

1. Full adder corresponding to least significant bit