CS501 Final Term Master File

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TABLE OF CONTENT ..................................................................................................................................................................... 1 INTRODUCTION. .......................................................................................................................................................................... 8 COURSE CONTENT: ............................................................................................................................................................................... 8 FAQ UPDATED VERSION. ........................................................................................................................................................... 10 Question: what is nested interrupt? ......................................................................................................................................... 10 Question: What is an interrupt mask? ...................................................................................................................................... 11 Question: What is memory mapped I/O ? ................................................................................................................................ 11 Question: What is Programmed I/O? ....................................................................................................................................... 11 Question: What is Virtual Memory? ......................................................................................................................................... 11 Question: Difference between Little Endian and Big Endian? .................................................................................................. 11 Question: Explain Booth's Algorithm with example. ................................................................................................................ 12 Question: How we identify the Address Mode of the Instructions ? ......................................................................................... 13 Question: Explain the bench mark programming ? .................................................................................................................. 13 Question: How a debugger disassemble the machine language? ............................................................................................ 14 Question: Why Data Dependence Distance is required for the Branch delays? ....................................................................... 14 Question: How are shift instructions useful? When do we use them? ..................................................................................... 14 Question: What is Data bus, Address bus and control bus? How these three are interrelated with MAR and MBR with each other. please explain with diagram ? ........................................................................................................................................ 14 Question: What is the difference between compiler and assembler? ...................................................................................... 15 Question: Sir what are the disadvantages of RICS machine architecture (as there are lot of disadvantages of CISC)? ........... 15 Question: Which one is better CISC or RISC? ............................................................................................................................ 15 Question: What is vex machine? .............................................................................................................................................. 16 Question: Tell me about Behavioral RTL ? What are its functions ? ......................................................................................... 16 Question: How can we utilize the functional parallelism ? ....................................................................................................... 16 Question: I want to know about PVM ( PARALLEL VIRTUAL MACHINE ) and MPI ( MESSAGES PASSING INTER FACE ). .......... 16 Question: What is Process - Level Concurrent Execution ? ....................................................................................................... 17 Question: What is difference between hardware debugger & software debugger? ................................................................ 17 Question: What is difference between concurrent and sequential statements? ...................................................................... 17 Question: What is FALCON-A ? ................................................................................................................................................. 18 Question: What is CPU register and processor register? .......................................................................................................... 18 Question: Explain the bench-mark programming ? .................................................................................................................. 18 Question: Define MIPS computer? ............................................................................................................................................ 18 Question: What difference between the logical address and effective address ? .................................................................... 18 Question: What is the meaning of ISA ? ................................................................................................................................... 19 Question: What are the " Emulators " and what are the function of emulators . Is it hardware tool? ..................................... 19 Question: Why CISC processors are faster in execution as compared to RISC? ........................................................................ 19 Question: Sir, please tell me that what is the SRC NOTATION? ................................................................................................ 19 Question: Sir what is an ISA ? What is ISA design and development ? ..................................................................................... 19 Question: RISC and CISC architectures? what is the difference between these two? ............................................................... 20 Question: What is Parallel Architecture and what is relation between Language & Parallel Architecture? ............................ 20 Question: Tell me about Parallel Processing & ILP Processing? Tell me also about the difference between these two? ......... 20 Question: What are Basic ILP Classes ? .................................................................................................................................... 21 Question: I want to know about RAW , WAR & WAW Dependencies. ..................................................................................... 21 Question: What is branching in advance architecture? ............................................................................................................ 21 Question: What is data Parallelism? ........................................................................................................................................ 22 Question: What are super scaler processors? .......................................................................................................................... 22 Question: Tell me something about the Processing of Control Transfer Instructions . ............................................................. 22 Question: Tell me something about Pipelined Processors and its Types . ................................................................................ 22 Question: What is meant by Pipelining & Repilication ? .......................................................................................................... 23 Question: Tell me about VILW Architecture in detail. ............................................................................................................... 23 Question: What are FLYNN's Classification and Proposed Classification? ................................................................................ 24 Question: What is Binary Semaphore and the Queue Semaphore? ......................................................................................... 24 Question: When CPU encounter an opcode of the instruction from the system memory, in what register does it hold that opcode? ..................................................................................................................................................................................... 25 Question: What is diffrence between encoding and decoding? ............................................................................................... 25 Question: Differentiate between CPU register and Cache Memory. ........................................................................................ 25 Question: How the processor knows that it has executed the instruction,who generate the control signal for that. What is exectiopn? ................................................................................................................................................................................. 25 Question: What are Dependencies Between the Instructions of a Program? .......................................................................... 26 GLOSSARY (UPDATED VERSION) ................................................................................................................................................ 26 Activation record : ..................................................................................................................................................................... 26 Address: ..................................................................................................................................................................................... 26 address bus : .............................................................................................................................................................................. 26 assembler : ................................................................................................................................................................................ 26 bus : ........................................................................................................................................................................................... 26 Reciproke of the clock cycle: ...................................................................................................................................................... 26 Clock period : ............................................................................................................................................................................. 27 clock rate : ................................................................................................................................................................................. 27 control bus : ............................................................................................................................................................................... 27 Control processor : ..................................................................................................................................................................... 27 data bus : ................................................................................................................................................................................... 27 handshaking : ............................................................................................................................................................................ 27 I/O devices : ............................................................................................................................................................................... 27 I/O ports : .................................................................................................................................................................................. 27 instruction set : .......................................................................................................................................................................... 27 mask : ........................................................................................................................................................................................ 28 multiprocessing : ....................................................................................................................................................................... 28 multitasking : ............................................................................................................................................................................. 28 opcode : ..................................................................................................................................................................................... 28 operand : ................................................................................................................................................................................... 28 parallel processing : ................................................................................................................................................................... 28 Pipelining: .................................................................................................................................................................................. 28 RISC : .......................................................................................................................................................................................... 28 Shared Memory : ....................................................................................................................................................................... 29 simulator : ................................................................................................................................................................................. 29 source operand : ........................................................................................................................................................................ 29 VLIW : ........................................................................................................................................................................................ 29 FALL 2011 LATEST PAPERS (CURRENT) ....................................................................................................................................... 29 PAPERS NUMBER 01 .................................................................................................................................................................. 29 MID-TERM PAST PAPERS (UPDATED VERSION) ......................................................................................................................... 30 If op-code is 0, the instruction is ‘add’. The values in register rb and rc are added and the result is stored in register ra........ 30

How can you define microprogram ? ........................................................................................................................................ 30

What is the utility of reset operation and when it is required? ................................................................................................. 31

What function is performed by the reset operation of a processor? What are the two types of reset operations? ................. 32

a. What is the advantage of a linker in the development of assembly language programs? ................................................... 32 b. Define term “Single stepping”. .............................................................................................................................................. 32 c. Define term “Type checking”. ................................................................................................................................................ 32 d. Define term “Instruction set”. ................................................................................................................................................ 33 e. Why computer logic design is different from classical logic design? ..................................................................................... 33

Q : DEFINE HARD RESET AND SOFT RESET OPERATIONS IN SRC................................................................................................ 33 Q : Write two pipelining problem and define them briefly. ....................................................................................................... 34 Q : What information is provided by the addressing modes of some processors? .................................................................... 34 Q : Eleborate Pre-Fetching Concept? ......................................................................................................................................... 34

Q : how we speed-up a computer? ............................................................................................................................................ 36 Q : Write execution time of an instruction(there was a description too) .................................................................................. 36 Q : Types of instructions ............................................................................................................................................................ 36 Q : How you represent register data field? ................................................................................................................................ 37 Write RTL structural lang that is shlr ra, rb, c2 .......................................................................................................................... 38

How many bits are included in one 1KByte ? ............................................................................................................................. 38 In which type of interrupts, the address of the service routine needs to be supplied externally by the device? ....................... 38

How many types of instructions are available in SRC? Name them. ......................................................................................... 38 What is the format of each of these instructions…….5marks .................................................................................................... 38 Write the Structural RTL for the call instruction for uni-bus data path ..................................................................................... 39 implementation. call ra, rb…………………..5 marks ...................................................................................................................... 39 Write the Structural RTL for the mov instruction for uni-bus data path .................................................................................... 41 implementation. mov ra, rb………………………..3 marks ............................................................................................................... 41 How many stages are in the pipelined version of SRC? Name them……..3 ................................................................................ 42 Marks ......................................................................................................................................................................................... 42

A question about to define the shift right instruction ? (2 Marks) ............................................................................................ 46 This command will shift a to right side 16 bits, and assign the value to z ................................................................................. 47 Structural RTL instructions definition? (3 Marks) ...................................................................................................................... 47

?????? ........................................................................................................................................................................................ 47 Define two hazards in pipelining and how can to overcome these. (5 Marks) .......................................................................... 47 Pipeline Hazards ........................................................................................................................................................................ 47 Classification of Hazards ........................................................................................................................................................... 47 Data Hazard Detection & Correction ......................................................................................................................................... 48