CS501 Final Term Quiz 3 July 2023 by Miss Mehwish

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1. Which is the last instruction of the ISR that is to be executed when the ISR terminates? Options:

• IRET
• IRQ
• NMI
• INT

Correct option: IRET

2. Where does the processor store the address of the first instruction of the ISR? Options:

• Interrupt handler
• Interrupt vector
• Interrupt vector table
• Interrupt service routine

Correct option: Interrupt vector

Q3. The third stage of the Pipelined version of SRC is:

• Instruction Fetch
• Register Write
• Memory Access
• ALU Operation

Correct option: ALU Operation

Q4. Interrupt-driven I/O is better than ______________.

• Polling
• Data Forwarding
• First In First Out
• Stall

Correct option: Polling

Q5. _____________ is an example of a synchronous communication error condition in which "0" is received instead of a stop bit (which is always a "1").

• Under-run error
• Overrun error
• Parity error
• Framing error

Correct option: Framing error

6. Every time you press a key, an interrupt is generated. This is an example of: Options:

• None of the given
• All of the given
• Software interrupt
• Hardware interrupt

Correct option: Hardware interrupt

Q7. The multiplexer ___________ is used to decide which value is transferred to be written back to the register file.

• MP5
• MP4
• MP2
• MP3

Correct option: MP2

Q8. The information about interrupt vector is given in 8-bits, from bit 0 to 7, which is translated to bit ___________ on the data bus.

• 0 to 7
• 11 to 18
• 11 to 16
• 16 to 23

Correct option: 0 to 7