CS501 Midterm Quiz by Quiz Monkey

CS501 quiz 2 Mid-term · Lec 11 to 20 · Junaid, Moaz and mid handout

Q1. Which are the two control unit design approaches?

Hardwired and micro programming…….confirm

2. The ___ control signal is used to enable the tri-stable buffers with the MBR.

MBR out…..confirm

3. The ____control signal to allow the IR read the value from the internal bus. Thus the instruction stored in the MBR is read into the instruction Register (IR).

Q4. Which of the following control signals is used to copy the contents of in bus on the out bus so it can be loaded into MAR?

C=B…..confirm

5. Which of the following control signals is used to contents of the memory buffer register are read out onto the out bus by means of applying this signal as it enables the read for the MBR.

MBRout…..confirm

6. Which of the following control signals is used this instruction will enable the write of the instruction register. Hence the instruction that is on the in bus is loaded into this register.
7. _______ is defined as the time required to process a single instruction.

Latency……confirm

8. The instruction fetch procedure generally takes _____ time step(s)

9. The syntax of the instruction “branch and link if zero” is

Brlzr ra, rb, rc….confirm · 10. The syntax of the instruction “branch if zero(brzr)” is · Brzr rb, rc…..confirm

Q11. Which of the following is responsible for generating signals for external events?

Interrupt generator…..confirm

12. _________ hazard occurs when an instruction attempts to access some data value that has not yet been updated by the previous instruction.

Data……confirm

13. In pipe-line processors, there should be a _________ data path so as not to complicate the flow of instructions and maintain the order of program execution.

Single……confirm

14. In pipe-line processors, there should be a ___________ port register file so that if the register write and read stages overlap, they can be performed in parallel.
15. Upon receiving the __ signal the SRC should perform a hard reset.

Strt…..confirm

16. Below given RTL description belongs to which stage of pipe-lining IR2 ← M [PC];

PC2 ← PC+4;

Instruction fetch…..confirm

17. Below given RTL description belongs to which stage of pipe-lining Z4 ← (I-s3: X3+Y3, brl3: X3, Alu3:X3 op Y3, MD4 ← MD3,

IR4 ← IR3;

ALU operation…..confirm

18. Below given RTL description belongs to which stage of pipe-lining Z5 ← (load4: M [Z4], ladr4~branch4~alu4:Z4), store4: (M [Z4] ← MD4),

IR5 ←IR4;

Memory access…..confirm

19. Below given RTL description belongs to which stage of pipe-lining regwrite5: (R[ra] ← Z5);

Write back…..confirm

20. The _______ instruction is completed once memory access has been made and the memory location has been written to