CS501 Midterm MCQs

Q1. of 10 ( Start time: 10:02:48 PM ) Total Marks: 1

What is the size of the memory space that is available to FALCON-A processor?

2^8 bytes

2^16 bytes

2^32 bytes 2^64 bytes

Q2. of 10 ( Start time: 10:03:58 PM ) Total Marks: 1

How can we refer to an instruction register (IR), of 16 bits (numbered 0 to 15) using RTL?

IR<16..0>

IR<15..0>

IR<16..1> IR<15..1>

Q3. of 10 ( Start time: 10:04:28 PM ) Total Marks: 1

What is the working of Processor Status Word (PSW)?

To hold the current status of the processor. To hold the address of the current process To hold the instruction that the computer is currently processing To hold the address of the next instruction in memory that is to be executed

Q4. of 10 ( Start time: 10:05:10 PM ) Total Marks: 1

What does the instruction “ldr R3, 58” of SRC do?

Q5. of 10 ( Start time: 10:06:34 PM ) Total Marks: 1

What is the instruction length of the FALCON-E processor?

8 bits 16 bits

32 bits

64 bits

Q6. of 10 ( Start time: 10:06:57 PM ) Total Marks: 1

Which one of the following portions of an instruction represents the operation to be performed?

Address

Opcode

Operand

Q8. of 10 ( Start time: 10:07:36 PM ) Total Marks: 1

For the __________ type instructions, we require a register to hold the data that is to be loaded from the

vu39

memory, or stored back to the memory

Jump Control

Q9. of 10 ( Start time: 10:08:08 PM ) Total Marks: 1

architect views the system for the description of system components and their interconnections?

Q10. of 10 ( Start time: 10:08:50 PM ) Total Marks: 1

Identify the opcode, destination register (DR), source registers (SA and SB i/e source register A and source register B) from the following example. ADD R1, R2, R3

Opcode= R1, DR=ADD, SA=R2, SB=R3

Opcode= ADD, DR=R1, SA=R2, SB=R3

Opcode= R2, DR=ADD, SA=R1, SB=R3 Opcode= ADD, DR=R3, SA=R2, SB=R1

Q1. of 10 ( Start time: 10:20:53 PM ) Total Marks: 1

Which one of the following circuit design levels is called the gate level?

Logic Design Level

Circuit Level Mask Level

Q2. of 10 ( Start time: 10:21:17 PM ) Total Marks: 1

The CPU includes three types of instructions, which have different operands and will need different representations. Which one of the instructions requires two source registers?

Jump and branch format instructions Immediate format instructions

Register format instructions

All of the above

Q5. of 10 ( Start time: 10:24:08 PM ) Total Marks: 1

P: R3 <- R5 MAR <- IR These two are instructions written using RTL .If these two operations is to occur simultaneously then which symbol will we use to separate them so that it becomes a correct statement with the condition that two operations occur simultaneously?

Parentheses () Arrow <- Colon : Comma ,

vu39

Q6. of 10 ( Start time: 10:25:09 PM ) Total Marks: 1

location (or another register) and are also called data movement?

What does the word ‘D’ in the ‘D-flip-Flop’ stands for?

Data

Digital

Dynamic Double

Q9. of 10 ( Start time: 10:27:24 PM ) Total Marks: 1

The instruction ---------------will load the register R3 with the contents of the memory location M [PC+56]

Add R3, 56 lar R3, 56

ldr R3, 56

str R3, 56

Q10. of 10 ( Start time: 10:28:07 PM ) Total Marks: 1

What is the instruction length of the FALCON-E processor?

8 bits 16 bits

32 bits

64 bits

Q2. of 10 ( Start time: 10:41:07 PM ) Total Marks: 1

Which one of the following are the code size and the Number of memory bytes respectively for a 2-address instruction?

4 bytes, 7 bytes 7 bytes, 16 bytes 10 bytes, 19 bytes 13 bytes, 22 bytes

Q3. of 10 ( Start time: 10:41:57 PM ) Total Marks: 1

Which one of the following portions of an instruction represents the operation to be performed?

Address

Opcode

Operand