CS501 Midterm Subjective

Solved Subjective · From Midterm Papers · DEC 01,2012 · PSMD01 · Spring 2012

1Two approaches for control unit.

Answer: (Page 150) Additionally, there are two different approaches to the control unit design; it can be either hard-wired or microprogrammed

2- What is micro program?

Answer: (Page 222) A collection of microinstructions is called a microprogram. These microprograms generate the sequence of necessary control signals required to process an instruction. These microprograms are stored in a memory called the control store.

3- structural RTL for mov ra, rb

Answer: (Page 164) 4Structural RTL and explanation for instruction fetch.

Answer: (Page 152) The instruction fetch procedure takes three time steps as shown in the table. During the first time step, T0, address of the instruction is moved to the Memory Address Register (MAR) and value of PC is incremented. In T1 the instruction is brought from the memory into the Memory Buffer Register (MBR), and the incremented PC is updated. In the third and final timestep of the instruction fetch phase, the instruction from the memory buffer register is written into the IR for execution. What follows the instruction fetch phase, is the instruction execution phase. The number of timing steps taken by the execution phase generally depends on the type and function of instruction. The more complex the instruction and its implementation, the more timing steps it will require completing execution. In the following discussion, we will take a look at various types of instructions, related timing steps requirements and data path implementations of these in terms of the structural RTL.

Spring 2012

Q1. Which register holds the address of the next instruction to be executed in the processor? (2 Marks)

Answer: (Page 28) The program counter (PC) that holds the address of the next instruction in memory that is to be executed.

Q2. What do you know about Machine Exception? (2 Marks)

Answer: (Page 197)

• Anything that interrupts the normal flow of execution of instructions in the processor is called an exception.
• Exceptions may be generated by an external or internal event such as a mouse click or an attempt to divide by zero etc.
• External exceptions or interrupts are generally asynchronous (do not depend on the system clock) while internal exceptions are synchronous (paced by internal clock)

Q3. How exception may be generated write the difference between external and internal exceptions? (3marks)

Answer: (Page 197) External exceptions or interrupts are generally asynchronous (do not depend on the system clock) while internal exceptions are synchronous (paced by internal clock)

Q4. Write the structure RTL description for mov instruction (3 Marks)

Answer: (Page 164) In mov instruction the data in register rb, which is the source register, is to be moved in the register ra, which is the destination register. In first three steps, mov instruction is fetched. In step T3 the contents of register rb are placed in buffer register C through the ALSU unit while in step T4 the buffer register C transfers the data to register ra through internal uni-bus.

Q5. Write the structure RTL description for shift instruction? (5 Marks)

Answer: (Page 157) Shift instructions are rather complicated in the sense that they require extra hardware to hold and decrement the count. For an ALSU that can perform only single bit shifts, the data must be repeatedly cycled through the ALSU and the count decremented until it reaches zero. This approach presents some timing problems, which can be overcome by employing multiple-bit shifts using a barrel shifter.

Spring 2012

Q - Write a structural RTL for Shift instruction for Uni-Bus data path implementation. shiftr ra, rb, c1 [5 Marks]

Answer: (Page 163)