Skip to content
VUBuddy

CS501 Grand Quiz by MCS Family

Advance Computer Architecture PDF 761 KBUpdated 23 Oct 2026
Quiz CS501 Grand Quiz by MCS Family PDF 761 KB
vubuddy.com
Type
Quiz
Course
CS501 Advance Computer Architecture
Size
PDF 761 KB
Updated
23 Oct 2026
Free download 0 of 3 used today
Download free · 761 KB

You get 3 free files a day on the website. Add the Chrome extension for 30 a day.

Unlimited downloads in the Android app Get it free on Google Play

Preview text

Text from pages 1, 2, 3 of 17. Download the file for all 17 pages.

CS501 GRAND QUIZ · SOLUTION MADE BY: · ARSL SHANI, AINA MALIK & MCS FAMILY GROUP TEAM

  1. The multiplexer------------is used to decide which value is transferred to be written back to the register file.
  • MP2
  • MP3
  • MP4
  • MP5

Q2. Which of the following condition is evaluated when executing the branch instruction “brzr R2, R1”?

  • If(R2==0)
  • If( R1 >0 )
  • If( R1==0)
  • If( R1 < 0)
  1. In case of SRC processor, bits---------of IR (instruction register) are reserved for the opcode.
  • 0 to 4
  • 11 to 15
  • 27 to 31
  • 59 to 63

Q4. Which of the given RTL description is used to represent “load instruction register” (ldr) instruction?

  • (op<4..0>=6): R[ra] rel
  • (op<4..0>=2): R[ra] M [rel]
  • (op<4..0>=2): M[disp] R [ra]
  • (op<4..0>=2): M[rel] R [ra]
  1. -------- Instruction is used to divide a register value by immediate value in FALCON-E processor.
  • div
  • idiv
  • divi
  • divim
  1. Which field of machine language instruction is the “type of operation” that is to be performed.
  • Op-code(or the operation code)
  • CPU register
  • Memory Cells
  • I/O Location

Q7. Which of the following control signal is NOT activated during instruction fetch operation?

  • PCout
  • LC
  • LMAR
  • Cout
  1. In case of FALCON-A------------ instruction are present which are not present in SRC processor.
  • create and destroy
  • in and out
  • open and close
  • read and write
  1. ----------- provides a temporary storage for the address of memory location to be accessed.
  • MAR
  • MBR
  • PC
  • LPC

Q10. Which of the following register is used to enable the tri-stable buffers with the MBR?

  • MBRout
  • MARout
  • LMBR
  • INC4

Q11. What functionality is performed by the instruction “str R8, 34” of SRC?

  • It will load the register R8 with the contents of the memory location M[34]
  • It will store the register R8 contents to the memory location M[34]
  1. Program Counter(PC) holds the memory address of:
  • Previous Instruction
  • Current Instruction
  • Next Instruction
  • Previous and Current Instruction

Q13. What is the working of Processor Status Word (PSW)?

  • To hold the current address of the process
  1. mul is the example of a(n)------------ operation.
  • Logic
  • Shift
  1. Control Signal for RTL “IR< ---MBR” will be---------
  • MBRout,LIR
  • PC< --C
  • PC< --MBR
  • PC< --IR

Q16. What does the instruction”ldr R3, 58” of SRC do?

  • It will store register R3 contents to the memory location M[PC+58]
  • It will store the value of register R3 at the relative address itself(PC+58)
  1. The status register of the 68000 has -------- condition codes.
  • 2
  • 3
  • 5
  • 8

Q18. Which of the instruction is used to load register from memory using relative address?

  1. For the ------ type instruction, we require a register to hold the data that is to be loaded from the memory, or stored back to the memory.
  • Jump
  • Control
  • L
  • Branch
  1. In a processor, ----------- is responsible for the synchronization of internal as well external events.
  • Memory Unit
  • Data Unit
  • Arithmetic & Logic Unit
  • Control Unit
  1. In CPU design, ------------ creates or forms the interface between the data path and control unit.
  • Buses
  • ALU
  • cache
  1. ----------- Control signal enables the input to the PC for receiving a value that is currently on the internal processor bus.
  • LPC
  • INC4
  • LC
  • Cout
  1. In SRC, the effective address is computed a run-time by adding a constant to value of---------- register.
  • FLAGS
  • IR
  • PC
  • Ra
  1. --------- control signal allow the content of the program counter register to be written onto the internal processor bus.
  • INC4
  • LPC
  • PCout
  • LC
  1. In ---------- instruction format of EAGLE processor, there is no field reserved for the operands.
  • Type V
  • Type Y
  • Type X
  • Type Z
  1. In Type C instruction of SRC, ---------- bits are allocated for constant values.
  • 16
  • 17
  • 21
  • 22
  1. A general purpose digital computer has --------- main components.
  • 2
  • 3
  • 4
  • 5
All CS501 files →
CS501 Advance Computer Architecture All CS501 handouts, past papers, quizzes and MCQs in one place. Open course page

Get more out of VUBuddy, for free

Android app Free on Google Play
  • Unlimited downloads
  • The explanation behind every MCQ answer
  • Study offline on slow data
Get the Android app
Chrome extension Free on the Chrome Web Store
  • 30 downloads a day instead of 3
  • Sign in and buy Pro Semester here
Add to Chrome

One Pro Semester membership works in both the extension and the app.