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CS501 Quiz 3 by Sunrise Zeeshan

Advance Computer Architecture PDF 4.7 MBUpdated 23 Oct 2026
Quiz CS501 Quiz 3 by Sunrise Zeeshan PDF 4.7 MB
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CS501 Advance Computer Architecture
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23 Oct 2026
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Cs-501 · Quiz no.3 · Lecture 23 to 30 · Sunrise Zeeshan

  1. Along with information bits we add up another bit which its called the bit. CRC Hamming Error Detection Parity
  2. Tri-state buffers are used for removing __________ Instruction collision bus collision Instruction contention bus contention

Q3. In which technique does the hardware directly access host memory for reading or writing independent of CPU?

Polling

  1. The main issue/s in error control is/are ________ Detection of Error Correction of Error Both Detection of Error and Correction of Error Avoidance of Error
  2. The source file of FALS!IM should contain_____ text only. Unicode ASCII ANSI UTF
  3. The directive______ is used to define vanables. .equ .org .db .sw
  4. human works with base 10 and computers work with base_______
  5. The information about interrupt vector is given in &-bits, from bit 0 to 7. which is translated to bit________ on the data bus. 16 to 23 11 to 18 0 to 7 8 to 15
  6. The_______ can be determined from the number of platters and the number of tracks. Speed of processing execution time storage capacity Latency
  7. The conversion of numbers from 4 representation in one base to another is known as. Radix Conversion Number Representation Decimal representation Hexadecimal Representation
  8. Every interrupt handler has an interrupt return (IRET) instruction, this instruction is an example of______ return. NEAR FAR SHORT RELATIVE
  9. A software routine performed when ani interrupt is received by the computer is called as -----— Interrupt Interrupt handler Exception Trap
  10. Identify the following type of serial communication error condition: “The prior character that was received was not still read by the CPU and is over written by a new recetved character.”

Overrun error Parity error Under-run error

  1. Taking control of the system bus for a few bus cycles is known as______ Bus Stealing Cycle Stealing Cycle Transfering None of given

Q15. What is the status of the ACKNLG# signal when a character is completely received by the printer?

It. goes from low to high It goes from high to low It toggles its state lt remains unaffected

Q16. How can you define an interrupt?

A process where an extemal device can spi e workinglof the microprocessor A process where memory can a a execution speed A process where an external device can get the attention of the microprocessor A process where input devices can takeover the working of the microprocessor

Q17. How Interrupt driven I/O is better than polling because?

Interrupt driver I/O is easy to design Interrupt driver |/O is enki defi version of Polling Interrupt driver I/O does not waste time on checking which device is available. Interrupt driven I/O is easy to program.

  1. For input ports, the incoming data should be placed on the data bus only during the I/O read bus cycle. For this Purpose_____ are used. Flip Flop Tri-state Buffers AND Gates Registers
  2. In the little-endian format exchanging data between computers, the data transmitted by one will be received in a “swapped” form by the other. Organized Signals Swapped Arranged

Q20. Which |/O technique will be used by a sound card that may need to access data stored in the computer's RAM?

Palling

  1. Select the parts of a hard disk. Data section and a trailer
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