CS501 Quiz 3 Set 3 by VU Topper RM

Cs-501 Important Mcq’s For Final Term

Solve By Vu_Toper RM

Q1. For any of the instructions that are a part of the instruction set of the SRC, there are cerain_________required; which may be used to select the appropriate

Register

Memory

Q2. FALCON-A processor bus has 16 lines or is 16-bits wide while that of SRC _____wide.

8-bits 16-bits

32-bits

64-bits

Q3. What is the instruction length of the FALCON-A processor

8-bits

16-bits

32-bits 64-bits

Q4. _________control signals enable the input to the PC for receiving a value that is currently on the internal processor bus.

LPC

INC4 LC I

Q5. Which one of the following is a bi-stable device, capable of storing one bit of information?

Decoder

Flip-Flop

Multiplexer Diplexer

Q6. Which instruction is used to store register to memory using relative address?

Q7. Which field of the machine language instruction is the “type of operation” that is to be performed?

Op-code (or the operation code)

CPU registers Momory cells I/O locations

Q8. The instruction ___________ will load the register R3 with the contenets of the m\emory location M [PC+56]

___Add R3, 56

___lar R3, 56

___ldr R3, 56

___str R3, 56

Q9. _______ operation is required to change the processor’s state to a known, defined value.

Change

Reset

Update

Q10. which type of instructions help in changing the flow of the program as and when required?

Control

Q1. of 10 ( Start time: 10:02:48 PM ) Total Marks: 1

What is the size of the memory space that is available to FALCON-A processor?

2^8 bytes

2^16 bytes

2^32 bytes 2^64 bytes

Q2. of 10 ( Start time: 10:03:58 PM ) Total Marks: 1

using RTL?

IR<16..0>

IR<15..0>

IR<16..1> IR<15..1>

Q3. of 10 ( Start time: 10:04:28 PM ) Total Marks: 1

What is the working of Processor Status Word (PSW)?

To hold the current status of the processor. To hold the address of the current process To hold the instruction that the computer is currently processing To hold the address of the next instruction in memory that is to be executed

Q4. of 10 ( Start time: 10:05:10 PM ) Total Marks: 1

What does the instruction “ldr R3, 58” of SRC do?

[PC+58]

Q5. of 10 ( Start time: 10:06:34 PM ) Total Marks: 1

What is the instruction length of the FALCON-E processor?

8 bits 16 bits

32 bits

64 bits

Q6. of 10 ( Start time: 10:06:57 PM ) Total Marks: 1

performed?

Address

Opcode

Operand

Q8. of 10 ( Start time: 10:07:36 PM ) Total Marks: 1

For the __________ type instructions, we require a register to hold the data that is to be loaded from the memory, or stored back to the memory

Jump Control

Q9. of 10 ( Start time: 10:08:08 PM ) Total Marks: 1

components and their interconnections?

Q10. of 10 ( Start time: 10:08:50 PM ) Total Marks: 1

Identify the opcode, destination register (DR), source registers (SA and SB i/e source register A and source register B) from the following example. ADD R1, R2, R3

Opcode= R1, DR=ADD, SA=R2, SB=R3

Opcode= ADD, DR=R1, SA=R2, SB=R3

Opcode= R2, DR=ADD, SA=R1, SB=R3 Opcode= ADD, DR=R3, SA=R2, SB=R1

Q1. of 10 ( Start time: 10:20:53 PM ) Total Marks: 1

Which one of the following circuit design levels is called the gate level?

Logic Design Level

Circuit Level Mask Level

Q2. of 10 ( Start time: 10:21:17 PM ) Total Marks: 1

The CPU includes three types of instructions, which have different operands and will need different representations. Which one of the instructions requires two source registers?

Jump and branch format instructions Immediate format instructions

Register format instructions

All of the above