Skip to content
VUBuddy

CS302 Final Term Current Papers 2018-2020

Digital Logic Design PDF 119 KBUpdated 23 Oct 2026
Final term past paper CS302 Final Term Current Papers 2018-2020 PDF 119 KB
vubuddy.com
Type
Final term past paper
Course
CS302 Digital Logic Design
Size
PDF 119 KB
Updated
23 Oct 2026
Free download 0 of 3 used today
Download free · 119 KB

You get 3 free files a day on the website. Add the Chrome extension for 30 a day.

Unlimited downloads in the Android app Get it free on Google Play

Preview text

Text from pages 1, 2, 3 of 4. Download the file for all 4 pages.

CS302 Current Final Term Papers 2018 To 2020 2020

Paper 1

Cs302 today’s paper 8 am 40 mcqs 10 subjectives Mcqs were mostly from past papers almost 30 from past

Applications of ROM atleast two

If address lines are 12 then how much memory locations will be access justify

Which register save address of top of stack if 2 and 3 are added to stack then what is incrementing/ decrementing value of that particular top stack register,justify why increment or decrement value of that register

Sum of product was given for A,B,C we have to made k.map of it and also map corresponding cells

One Flip flop was given we have to name it

3 bit a synchronous up counter was given we have to connect 3rd flip flop with second

Sum term was given we have to make expression from it

Moore machine table was given we have to made state diagram from it

4-bit Parallel In/Serial Out Shift register was given we have to connect some of states

Timing diagram of any flip flop was given we have to make output Q of it

Paper 2

Today CS302 paper. MCQS were from Moaaz Solved Past Papers. Jo k ma ne sath me attach kr di hai PDF, Aur baqi questions ye aye thy.

Q1. Give three guidelines for the selection of state assignment?

Q2. Write down the names of the two basic operations which are performed on memory?

Q3. What is the difference between combination circuit & sequential Circuit?

Q4. What is the difference between RAM & DRAM with respect to their circuitry?

Q5. How the information is represented in the digital systems? what are the different types of information handle by Digital Systems?

Q6. Draw diagram for 74HC163 4-bit synchronous counters to form a signle cascade decade counter?

Q7. Draw block diagram of Rotate Right Operation?

Q8. Write atleast three components used in FlashA/D converter circuit?

Q9. Truth table of J.K Flip Flop with Asynchronouse input?

  1. Ye ma bhool gya, koi ABEL represetation sy kuch draw krna tha.

Best of Luck to All Of You.

2019

Paper 1

Cs302 paper aajka 90% mcqs moazz file se thay subjective me memory se related question thay S-R latch se related thay.

Paper 2

Cs302 mostly from past papers (mcq's and subjective) from waqar and moaz files.. Long short...Flip flop diagrams. ...circuit diagrams...advantages of digital system

Paper 3

Cs302 final term paper. 40 mcqs Mcqs 80% from past. 5 question 3 marks k .5 question 5 marks k.

  1. circuit given tha us ka function btna tha.
  2. SRAM ka circuit bnna tha.
  3. D/A converter ki resolution 3 bits circuit ki bits ki percentage btnai thi.
  4. race condition and clock skew defination
  5. mealy machine moore machine me difference.
  6. using state reduction process and reduce tha state as possible .table given tha.
  7. proformance characteristics of analog to digital converter k names likhny thy.
  8. main difference b/w s-R latch and d latch .how we convert SR latch into D latch.
  9. A'B+B'C +A'C sop expression map into karnugh map
  10. write down the test vector table of up/down counter with given information. Inputs are clear ,X ,Clock Output Q0,Q1,Q2 If clear=0 then counter Reset to value 000 X= 1 then count up

Paper 4

today my cs 302 paper 20 mcqs from moaaz past file binary code diya howa tha usko hexadecimal main convert karna tha can we reverse counter true or not? applications of j_k edge trigged flip flop state reduction 3 bit up down counter ki state di hoi thi thi next state external input py find karni thi 4 bit down counter ki next 4 clock py state find karni thi decimal to bcd diagram di hoi thi usko 7 bit main change karna tha

All CS302 files →
CS302 Digital Logic Design All CS302 handouts, past papers, quizzes and MCQs in one place. Open course page

Get more out of VUBuddy, for free

Android app Free on Google Play
  • Unlimited downloads
  • The explanation behind every MCQ answer
  • Study offline on slow data
Get the Android app
Chrome extension Free on the Chrome Web Store
  • 30 downloads a day instead of 3
  • Sign in and buy Pro Semester here
Add to Chrome

One Pro Semester membership works in both the extension and the app.