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CS302 Final Term Quiz 3 File 2 July 2023 by Miss Mehwish

Digital Logic Design PDF 666 KBUpdated 23 Oct 2026
Final term past paper CS302 Final Term Quiz 3 File 2 July 2023 by Miss Mehwish PDF 666 KB
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Final term past paper
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CS302 Digital Logic Design
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PDF 666 KB
Updated
23 Oct 2026
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ِِبِسْم · ِِالل · ِِالرَّحْمٰن · ِِالرَّحِيْم

Q1. Two 2-input, 4-bit multiplexers 74X157 can be connected to implement a ____ multiplexer. Options:

  1. 4-input, 16-bit
  2. 2-input, 8-bit
  3. 4-input, 8-bit
  4. 2-input, 4-bit

Correct option: a) 4-input, 16-bit

Q2. ____________ is said to occur when multiple internal variables change due to change in one input variable.

  1. Clock Skew
  2. Race condition
  3. Hold delay
  4. Hold and Wait

Correct option: b) Race condition

Q3. The latch is said to be in logic _________ state when Q=1 and Q'=0, and it is in the logic low state when Q=0 and Q'=1.

  1. Low
  2. High
  3. Constant
  4. Zero

Correct option: b) High

Q4. Asynchronous means that ___________.

  1. Each flip-flop after the first one is enabled by the output of the preceding flip-flop
  2. Each alternative flip-flop after the first one is enabled by the output of the preceding flip-flop
  3. Each flip-flop is enabled by the output of the preceding flip-flop
  4. Each flip-flop except the last one is enabled by the output of the preceding flip-flop

Correct option: c) Each flip-flop is enabled by the output of the preceding flip-flop

Q5. A _________ can not operate without a memory element.

  1. Unit
  2. Clock
  3. Cell
  4. Counter

Correct option: d) Counter

Q6. __________ flip-flops are obsolete now.

  1. Edge-triggered
  2. T-Flipflop
  3. Master-Slave
  4. D-Flipflop

Correct option: c) Master-Slave

Q7. __________ occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.

  1. Clock Skew
  2. Ripple Effect
  3. Race condition

Correct option: a) Clock Skew

Q8. An Asynchronous Down-counter is implemented (Using J-K flip-flop) by connecting ________Q output of all flip-flops to the clock input of the next flip-flops.

  1. Q' output of all flip-flops to clock input of next flip-flops
  2. Q output of all flip-flops to J input of next flip-flops
  3. Q' output of all flip-flops to K input of next flip-flops

Correct option: C) Q' output of all flip-flops to K input of next flip-flops Q' output of all flip-flops to K input of next flip-flops

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