CS302 Final Term Past Paper Fall 2003

FINALTERM EXAMINATION · SEMESTER FALL 2004 · CS302-Digital Logic Design (S1)

2. 2. Calculators are NOT allowed.
3. 4. Circuit Diagrams, Equations and Truth Tables should be clear. Write down all the steps in Subjective Questions. Marks will be deducted for missing steps.

Question · Total · Marks

Q1. Marks: 8+8

1. Convert each of the following POS expression to minimum SOP expression using a Karnaugh Map. A

B A B C B C D A B C D b) Convert the decimal numbers 78 and 34 into Octal. Using octal addition, add the two numbers and convert the octal result back into decimal and verify the answer.

Q2. Marks: 8

Draw the timing diagram of QA, A Q , QB and B Q . Assume the Positive edge triggering. It is required to construct a memory with 256 words, 16 bits per word. Cores are available in a matrix of 16 rows and 16 columns. a) How many matrices are needed? b) How many flip-flops are in the address and buffer registers? c) How many cores receive current during a read cycle? d) How many cores receive at least half-current during a write cycle?

Q5. Marks: 8

Show the data output waveform for a 4-bit register with the parallel input data and the clock and SHIFT LOAD waveform given in the figure. The serial data input (SER) is a 0. The parallel data inputs are D0=1, D1=0, D2=1, D3=0 as shown. Develop the data-output waveform in relation to the inputs.

C SHIFT/LOAD

CLK SER D0 D3 D2 D1

Data out

CLK

SHIFT/LOAD

Data out Q3

Q6. Marks: 10

Implement a 4-bit Johnson Counter using J-K flip-flops

Q7. Marks: 8

Briefly answer the following questions: a) What does sampling mean? b) Why you must hold a sampled value? c) If the highest frequency component in an analog signal is 20kHz, what is minimum sample frequency? d) What determines the accuracy of quantization process?