CS302 Final Term Past Paper Spring 2005

MIDTERM EXAMINATION · SEMESTER SPRING 2005 · CS302-Digital Logic Design (S1)

2. 2. Calculators are NOT allowed.
3. 4. Circuit Diagrams, Equations and Truth Tables should be clear. Write down all the steps in Subjective Questions. Marks will be deducted for missing steps.

Question

Q1. Marks: 2+2+2+2+2=10

Select the best possible choice.

Q1. The OR gate performs Boolean ___________.

1. multiplication
2. subtraction
3. division
4. addition

Q2. How many states does a modulus-4 counter have?

1. 1
2. 2
3. 4
4. 16

Q3. How will a serial in/serial out shift register accept data serially?

1. one bit at a time
2. 8 bits at a time
3. only after a load pulse
4. only after being cleared

Q4. The invalid state of an SR latch occurs when

1. S=1,R=0
2. S=0,R=1
3. S=1,R=1
4. S=0,R=0

Q5. The storage cell in SRAM is

1. a flip –flop
2. a capacitor
3. a fuse
4. a magnetic domain

Q2. Marks: 12+2+2=16

1. Simplify the Boolean function using k-map and draw the circuit diagram.

(1,3,5,6,7) F x y z = ∑

b) Define JEDEC file c) What is 2’s complement of 0011 1001?

Q3. Marks: 10

Draw the circuit diagram of the 4x1 Multiplexer. Also write down its truth table?

Q4. Marks: 20

Design a 2-bit count-down counter. This is a sequential circuit with two flip flops and one input x. when x=0 the state of flip flop doesn’t change. When x=1 the state sequence is 11, 10.01,00,11 and repeat.

Q5. Marks: 12

For the data input and clock in figure, determine the states of each flip-flop in the shift register for the diagram and show the Q waveforms. Assume that the register contains all 1s initially.

C D

C D

C D

C D Serial

CLK FF0 FF1 FF2 FF3 Serial data output

Serial data output