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CS302 Midterm Past Papers by Junaid

Digital Logic Design PDF 1.6 MBUpdated 23 Oct 2026
Midterm past paper CS302 Midterm Past Papers by Junaid PDF 1.6 MB
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Midterm past paper
Course
CS302 Digital Logic Design
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PDF 1.6 MB
Updated
23 Oct 2026
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Q1. Which of the following is a volatile memory?

  1. PROM
  2. DRAM
  3. EPROM
  4. EEPROM
  5. ________ is used when the output is connected back to the input of the PAL or if the output pin is used as an input only.
  6. Combinational Input/output
  7. Combinational Output
  8. Combinational Input AL-JUNAID INSTITUTE OF GROUP
  9. Programmable polarity
  10. The AND Gate performs a logical ________ function.
  11. Addition
  12. Subtraction
  13. Multiplication
  14. Division
  15. The Adjacent 1s Detector accepts 4-bit inputs. If ________ adjacent 1s are detected in the input, the output is set to high.
  16. 2
  17. 4
  18. 1
  19. 0

Q5. In the keyboard encoder, how many times per second does the ring counter scan the key board?

  1. 600 scans/second
  2. 625 scans/second
  3. 650 scans/second
  4. 700 scans/second
  5. The FAST Model Page Access allows ________ memory read and access times when reading successive data values stored in consecutive locations on the same row.
  6. Slow
  7. Faster
  8. Medium
  9. Modern
  10. GAL can be reprogrammed as instead of fuses E2CMOS logic is used which can be programmed to connect a ________ with a ________.
  11. column, row
  12. row, column
  13. column, column
  14. row, row

Q8. Which of the following Output Equations determines the output of the State Machine?

  1. MIN = Q0Q1
  2. MAX = Q0Q1EN
  3. MIN = Q0Q1EN
  4. MAX = Q1EN
  5. The maximum value, represented by a single hexadecimal digit is ________.
  6. "E"
  7. "F"
  8. "G"
  9. "H"

10. If the voltage drop across the active load is 0 volts due to absence of current the comparator output is a

  1. 0
  2. 1

11. The Static Ram (SRAM) is non-volatile and is not a ________ density memory as a latch is required to store a single bit of information.

  1. Low
  2. High
  3. Medium
  4. Hot

12. DE Morgan’s two theorems prove the equivalency of the NAND and ________ gates and the NOR and ________ gates respectively.

  1. Negative-OR, Negative-AND
  2. Negative-AND, Positive-OR
  3. Positive-OR, Negative-AND
  4. Positive-OR, Positive-AND

13. Two signals ________ and ________ provide the timing inputs to the State Machine.

  1. NSSR and EWSR
  2. LTIME and STIME
  3. PTIME and QTIME
  4. NSGrn and NSYel

14. The 74HC163 is a 4-bit Synchronous counter, it has ________ data output pins.

  1. 2
  2. 4
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