CS302 MCQs Lectures 23-45

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Dear Students,

In this post we are providing you CS302 Quiz-2 Solution Fall 2022 (21 to

41. 100% correct or right solution.

Semester Quiz # 02

Dear Students,

It is to inform that Semester Quiz # 02 has been opened today and it will remain open for 48 hours only. You are strongly advised to take this activity seriously and make sure to submit the quiz within the given date. No quiz submission requests will be entertained later in any case due to any reason.

CS302 Quiz File

To write data to the memory the memory the write cycle is initiated by

Applying the address signals

The counter states or the range of the number of a counter is determined by the formula(“n” represented the total number of flip-flops ) 2 raise to power n

THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT __________ GATE

OR

A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BYTHE MANUFACTURER.

TRUE

in sequential circuits memory elements are connected with___________.

common clock

A synchronous decade counter will have _______ flip-flops

the terminal count of a modulus -13 binary counter is

1101

The alternate solution for a multiplexer and a register circuit is _________

Parallel in / Serial out shift register

A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.

machine?

The CONSTATE.CLK = Clock is used to indicate that the ________ state variables change on a clock transition. CONSTATE

Memory is arranged in ________.

two-dimensional manner

The n flip-flops store ________ states.

2^n

PALs tend to execute ________ logic.

SOP

In DRAM read cycle R /Wsignal is activated to read data which is made available on the ________ data line.

D(OUT)

A SOP expression can be implemented by an ________ combination of gates.

AND-OR

Why demultiplexer is called a data distributor?

Single input to Single Output

If the number of samples that are collected is reduced by half, the reconstructed signal will be ________ from/to the original.

Same

The AND Gate performs a logical ________ function.

Division

The next state table for REQ1, FLOOR1 and OPEN inputs indicates that the ________ can be pressed at any time either on the first floor or the second floor in elevator.

REQ1