- Type
- Quiz
- Course
- CS302 Digital Logic Design
- Size
- PDF 1.1 MB
- Updated
- 23 Oct 2026
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Four
1. In case of cascading Integrated Circuit counters, the enable inputs and RCO of the Integrated
Circuit counters allow cascading of multiple counters together.
1. True
2. False
2.
Two types of memories namely the first in-first out (FIFO) memory and last in first out
(LIFO) are implemented using
1. Shift Registers
2. Circular Buffers
3. Ring Buffers
4. Reduce Registers
3.
The Synchronous SRAM also has a Burst feature which allows the Synchronous SRAM to
single address.
1. One
2. Two
3. Three
4.
4.
When the transmission line is idle in an asynchronous transmission
1. It is set to logic low
3. It remains in previous state
4. State of transmission line is not used to start transmission
5.
A multiplexer with a register circuit converts
1. Serial data to parallel
3. Serial data to serial
4. Parallel data to parallel
- It is set to logic high
- Parallel data to serial
6.
is used when the output is connected back to the input of the PAL or if the
output pin is used as an input only.
1. Combinational Input/Output
2. Combinational Output 3.
Combinational Input
- Programmable polarity
7.
The terminal count of a 4-bit binary counter in the UP mode is
12. Implementation of Latch is required almost
transistor.
1.
Two
2.
Four
3.
Six
4. Eight
corresponding to the product term (Minterm) present in the expression.
- 0
- 1
3. x (don't care condition)
4. Any of given option depending on SOP term
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