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CS302 Quiz 1 Updated Set 2 by Attiq Kundi

Digital Logic Design PDF 1.1 MBUpdated 23 Oct 2026
Quiz CS302 Quiz 1 Updated Set 2 by Attiq Kundi PDF 1.1 MB
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CS302 Digital Logic Design
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PDF 1.1 MB
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23 Oct 2026
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CS302 Quiz-1 BY Attiq Kundi · ON YOU TUBE CS302 100 % · CORRECT MCSQ · AND Many MoRe

1. In case of cascading Integrated Circuit counters, the enable inputs and RCO of the Integrated

Circuit counters allow cascading of multiple counters together.

1. True

2. False

2.

Two types of memories namely the first in-first out (FIFO) memory and last in first out

(LIFO) are implemented using

1. Shift Registers

2. Circular Buffers

3. Ring Buffers

4. Reduce Registers

3.

The Synchronous SRAM also has a Burst feature which allows the Synchronous SRAM to

read or write up to · location(s) · using · a

single address.

1. One

2. Two

3. Three

4.

4.

When the transmission line is idle in an asynchronous transmission

1. It is set to logic low

3. It remains in previous state

4. State of transmission line is not used to start transmission

5.

A multiplexer with a register circuit converts

1. Serial data to parallel

3. Serial data to serial

4. Parallel data to parallel

  1. It is set to logic high
  2. Parallel data to serial

6.

is used when the output is connected back to the input of the PAL or if the

output pin is used as an input only.

1. Combinational Input/Output

2. Combinational Output 3.

Combinational Input

  1. Programmable polarity

7.

The terminal count of a 4-bit binary counter in the UP mode is

12. Implementation of Latch is required almost

transistor.

1.

Two

2.

Four

3.

Six

4. Eight

13. For a Standard SOP expression, a · is · placed · in · the · cell

corresponding to the product term (Minterm) present in the expression.

  1. 0
  2. 1

3. x (don't care condition)

4. Any of given option depending on SOP term

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