CS501 Final Term Highlighted Handouts by Masters

Those five stages

Pipelined SRC

1. Instruction Fetch
2. Instruction decode/operand fetch

program counter is held in PC2 When the register values have been read, the first register value

After the instruction has been executed in the ALU, the register Z4 holds the result. The op-code Vincent P. Heuring & Harry F. Jordan Chapter 5 Computer Systems Design and Architecture 5.1.3

Summary

Pipelined Version of the SRC

In this lecture, a pipelined version of the SRC is presented. The SRC uses a five-stage pipeline. are given below:

As shown in the next diagram, there are several registers between each stage.

and the

These will be shown at appropriate places in later figures.

The number after a particular register name indicates the stage where the value of this register is used. There are also two op-code and ra are passed into IR5 while the stored back into the register, r Z5 holds the value to be During the write back stage, the registe and ra are passed on to IR4. a store to memory instruction, MD3 holds the register value to be stored. If it is IR3 holds the opcode and ra. and the second register value is stored in Y3 is stored in X3,

5. Register write
6. Memory access
7. ALU operation

separate memories and several multiplexers involved in the pipeline operation. incremented value of the After the instruction has been fetched, it is stored in IR2 Control Signals for Pipelined SRC Pipelined Version of the SRC

multiplexer 5 stages of pipeline The ALU function is determined by decoding the op-code bits. stages.

1. ALU Instructions
2. Load/Store instructions
3. Branch Instructions

ALU instructions are usually of the form:

op-code ra, rb, rc As mentioned earlier, the

We will now discuss how to design a common pipeline for all three categories of instructions.

1. ALU instructions

or

In the diagram shown, X3 is loaded with operand value from the register file. Y3 is loaded with either a register value from the register file or a constant from the instruction. The operands are then available to the ALU.

back stage. The result of the ALU and then stored in the destination register in the register write . Note that Z5, IR3, IR4, and IR5 are not shown explicitly in the figure. The purpose of not including these registers is to keep the drawing simple. However, these registers will transfer values as op-code ra, rb, constant.

There is no activity in the memory access stage for ALU instructions operation is stored in register Z4 X3 and Y3 are temporary registers to hold the values between pipeline SRC instructions fall into the following three categories: nd the incremented value of the PC is loaded in PC2. In

2. Load/Store instructions

Load/Store instructions are usually of the form:

op-code ra, constant(rb)

the relative addressing mode, and c2 is transferred to Y3 for the displacement addressing mode. instructions progress through the pipeline. This comment also applies to some other figures in this discussion.

next stage, a the the relative addressing mode is used, or the value in rb if the displacement addressing mode is used. Similarly,

The store instruction is completed once memory access has been made and the memory location has been written to. The load instruction is completed once the loaded value is transferred back to the register file. The following figure shows the schematic for a load instruction. A similar schematic can be drawn for the store instruction. C1 is transferred to Y3 for X3 is loaded with the value in PC2 if The instruction is loaded into IR2