CS501 Highlighted Handouts by Mickey Ch

Table of Contents

FALSIM............................................................................................................... 4

Introduction................................................................................................................... 19

Instruction Set Architecture ......................................................................................... 32

Introduction to SRC Processor ..................................................................................... 44

ISA and Instruction Formats......................................................................................... 50

Description of SRC in RTL .......................................................................................... 64

RTL Using Digital Logic Circuits ................................................................................ 73

Design Process for ISA of FALCONA ........................................................................ 87

ISA of the FALCONA.................................................................................................. 91

Description of FALCONA and EAGLE using RTL ........................................104

The FALCONE and ISA Comparison.........................................................................124

CISC and RISC ...........................................................................................................148

CPU Design .................................................................................................................149

Structural RTL Description of the FALCONA .......................................................... 156

External FALCONA CPU ...........................................................................................162

Logic Design and Control Signals Generation in SRC......................................171

Control Unit Design......................................................................................................183

Machine Reset and Machine Exceptions .....................................................................193

Pipelining .....................................................................................................................199 Lecture 19 .........................................................................................................................206 Pipelined SRC...............................................................................................................206

Hazards in Pipelining....................................................................................................212 Lecture 21 ........................................................................................................................ 218 Instruction Level Parallelism .......................................................................................218

Advanced Computer Architecture-CS501

Microprogramming..........................................................................................222

I/O Subsystems...........................................................................................................232

Designing Parallel Input and Output Ports.................................................................243

Input Output Interface.................................................................................................252

Programmed I/O..........................................................................................................262

Interrupt Driven I/O....................................................................................................273

Interrupt Hardware and Software................................................................................282

FALSIM......................................................................................................................295

Interrupt Priority and Nested Interrupts......................................................................310

Direct Memory Access (DMA)..................................................................................316

Magnetic Disk Drives.................................................................................................323

Error Control...............................................................................................................328

Number Systems and Radix Conversion....................................................................333

Multiplication and Division of Integers......................................................................340

Floating-Point Arithmetic...........................................................................................346

Components of memory Systems...............................................................................350

Memory Modules..............................................................................................355

The Cache...................................................................................................................358

Virtual Memory..........................................................................................................364

Numerical Examples of DRAM and Cache.....................................................371

Performance of I/O Subsystems.......................................................................380

Networks..........................................................................................................386

Communication Medium and Network Topologies........................................391

Last Modified: 24-Nov-11

Reading Material · Handouts · Summary · 1. Introduction to FALSIM · 2. Preparing source files for FALSIM · 3. Using FALSIM · 4. FALCONA assembly language techniques · FALSIM · 1. Introduction to FALSIM:

FALSIM is the name of the software application which consists of the

FALCONA assembler and the FALCONA simulator. It runs under · Windows XP. · FALCON(A Assembler:

Figure 1 shows a snapshot of the FALCONA Assembler. This tool loads a FALCONA assembly file with a (.asmfa) extension and parses it. It shows the parse results in an error log, lets the user view the assembled fileAs contents in the file listing and also provides the features of printing the machine code, an Instruction Table and a Symbol Table to a FALCONA

listing file. It also allows the user to run the FALCONA Simulator.

The FALCONA Assembler has two main modules, the 1stpass and the 2ndpass. The 1stpass module takes an assembly file with a (.asmfa) extension and processes the file contents. It then creates a Symbol Table which corresponds to the storage of all program variables, labels and data

values in a data structure at the implementation level. If the 1stpass

completes successfully a Symbol Table is produced as an output, which is