CS501 Midterm Solved Papers Mega File

MIDTERM EXAMINATION · Spring 2010 · CS501- Advance Computer Architecture (Session - 5) · Time: 60 min Marks: 38

Q1. What is the instruction length of the SRC processor? (1 marks)

8 bits

16 bits

32 bits

64 bits

Q2. Which one of the following is the memory organization of FALCON-E (1 marks)

processor?

28 * 8 bits

216 * 8 bits

232 * 8 bits

264 * 8 bits

Q3. “If P = 1, then load the contents of register R1 into register R2”. This statement can be written in RTL as: (1 marks)

R1 ¬ R2

P: R1 ¬ R2

P: R2 ¬ R1

P: R2 ¬ R1, P: R1 ¬ R2

Q4. The instruction ---------------will load the register R3 with the contents of the memory (1 marks)


Add R3, 56 
lar R3, 56


ldr R3, 56


str R3, 56

Q5. ----------are faster than cache memory ≡ Accumulator register (1 marks)

≡ CPU registers

≡ I/O devices

≡ ROM

Q6. P: R3 ¬ R5 (1 marks)

MAR ¬ IR

These two are instructions written using RTL .If these two operations is to occur simultaneously then which symbol will we use to separate them so that it becomes a correct statement with the condition that two operations occur simultaneously?

Arrow ¬

Colon :

Comma ,

Parentheses ()

Q7. Prefetching can be considered a primitive form of------------- (1 marks)


Multi-processing


Self-execution


Exception

Q8. The processor must have a way of saving information about its state or context so that it can be restored upon return from the ------------- 
Exception (1 marks)


Function


Stack


Thread

Q9. Which one of the following circuit design levels is called the gate level? (1 marks)


Logic Design Level


Circuit Level


Mask Level

Q10. __________ enable the input to the PC for receiving a value that is currently on the internal processor bus. (1 marks)

LPC
INC4
LC
Cout

Q11. ________ operation is required to change the processor’s state to a known, defined value. (1 marks)

Change