CS302 Final Term Solved MCQs with References

Objectives

40 Marks

1. The address from which the data is read, is provided by _______

•  Depends on circuitry
•  RAM

 Microprocessor

2. The best state assignment tends to ___________.

•  Maximizes the number of state variables that don’t change in a group of related states

 Minimizes the number of state variables that don’t change in a group of related states

•  Minimize the equivalent states

3. The total amount of memory that is supported by any digital system depends upon ______

•  The organization of memory
•  The structure of memory
•  The size of decoding unit

 The size of the address bus of the microprocessor

4. The expression F=A+B+C describes the operation of three bits _____ Gate.

•  OR
•  AND
•  NOT
•  NAND

5. The output of this circuit is always ________.

•  1
•  0
•  A

6. A Nibble consists of _____ bits

•  2
•  4

Digital Logic Design (CS302) · Final Term Exam · Total marks = 80 · Date 17th of Feb 2018

•  8
•  16

7. In asynchronous transmission when the transmission line is idle, _________

•  It is set to logic low
•  It is set to logic high
•  Remains in previous state
•  State of transmission line is not used to start transmission

8. The _____________ input overrides the ________ input

•  Asynchronous, synchronous
•  Synchronous, asynchronous
•  Preset input (PRE), Clear input (CLR)
•  Clear input (CLR), Preset input (PRE)

9. In a sequential circuit the next state is determined by ________ and _______

•  State variable, current state
•  Current state, flip-flop output

 Current state and external input

•  Input and clock signal applied

10. A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.

•  1
•  2
•  4
•  8

11. The 4-bit 2’s complement representation of “+5” is _____________

•  1010
•  1110
•  1011
•  0101

12. Stack is an acronym for _________

•  FIFO memory

 LIFO memory

•  Flash Memory
•  Bust Flash Memory

13. FIFO is an acronym for __________

 First In, First Out

•  Fly in, Fly Out
•  Fast in, Fast Out

14. DRAM stands for __________

 Dynamic RAM

•  Data RAM
•  Demoduler RAM

15. The alternate solution for a DE multiplexer-register combination circuit is _________

•  Parallel in / Serial out shift register
•  Serial in / Parallel out shift register
•  Parallel in / Parallel out shift register
•  Serial in / Serial Out shift register

16. In a state diagram, the transition from a current state to the next state is determined by

 Current state and the inputs

•  Current state and outputs
•  Previous state and inputs
•  Previous state and outputs

17. ____________ Counters as the name indicates are not triggered simultaneously.

•  Asynchronous
•  Synchronous
•  Positive-Edge triggered
•  Negative-Edge triggered

18. "A + B = B + A" is __________

•  DE Morgan’s Law
•  Distributive Law

 Commutative Law

•  Associative Law

19. For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will ______ if the clock goes HIGH.

•  Toggle
•  Set
•  Reset
•  Not change