CS302 Final Term MCQs

CS302 Final Term Mega File

A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.

1. 1
2. 2
3. 4
4. 8

Q2. In a sequential circuit the next state is determined by ________ and _______

1. State variable, current state
2. Current state, flip-flop output
3. Current state and external input
4. Input and clock signal applied

Q3. The divide-by-60 counter in digital clock is implemented by using two cascading counters:

1. Mod-6, Mod-10
2. Mod-50, Mod-10
3. Mod-10, Mod-50
4. Mod-50, Mod-6

Q4. In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.

1. True
2. False

Q5. The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.

1. Set-up time
2. Hold time
3. Pulse Interval time
4. Pulse Stability time (PST)

Q6. 74HC163 has two enable input pins which are _______ and _________

1. ENP, ENT
2. ENI, ENC
3. ENP, ENC
4. ENT, ENI

The bolean expression A + BC equals

(A ' + B )( A ' + C) (A + B )( A + C ) (A + B )( A' + C ) none of the above

Adjacent 1 s detector circuit will have active high output for the input

0101 1010 0011 0001

required for selecting eight inputs ?

Which of the number is not a representative of hexadecimal system

1234 ABCD

1001

DEFH

In case of cascading Integrated Circuit counters, the enable inputs and RCOof the Integrated Circuit counters allow cascading of multiple counters together

True

False

High level Noise Margins ( VNH ) of CMOS 5 volt series circuits is

1. 3 V
2. 5 V

0 . 9 V

3. 3 V

To get the answer “ 1 ” in Boolean addition of three variables , ________

All three variables must be 1

One of the variables must be 1

All three variables must be 0 Any two variables must be 1

has _______ cells for min or max terms

________ is invalid number of cells in a single group formed by the adjacent cells in K - map

The boolean expression A + B' + C is

a sum term

a complemented term

Consider A= 1 ,B = 0 , C= 1 . A, B and C represent the input of three bit NAND gate the output of the NAND gate will be _____

Zero One Undefined No output as input is invalid

The Binary number 1011 .101 has an