CS302 Final Term Solved MCQs with References by Students

CS302 Digital Logic Design · Final Term Papers Solved MCQs with reference by · Virtualians Social Network · FINALTERM EXAMINATION Spring 2011

Q1. clock signal(s) will be required to shift the value completely out of the register. (1 marks)

1. 1
2. 2
3. 4
4. 8 (Page 356)

Correct answer: 8 (Page 356)

Q2. In a sequential circuit the next state is determined by (1 marks)

and

1. State variable, current state
2. Current state, flip-flop output
3. Current state and external input

Correct answer: Current state and external input

(Page 318)

1. Input and clock signal applied

Q3. The divide-by-60 counter in digital clock is implemented by using two cascading counters: (1 marks)

1. Mod-6, Mod-10

(Page 299)

1. Mod-50, Mod-10
2. Mod-10, Mod-50
3. Mod-50, Mod-6

Q4. In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained. (1 marks)

1. True

(Page 221)

Q5. The minimum time for which the input signal has to be maintained at the input of flip-flop is called (1 marks)

of the flip-flop.

1. Set-up time
2. Hold time (Page 242)
3. Pulse Interval time
4. Pulse Stability time (PST)

Correct answer: Hold time (Page 242)

Q6. 74HC163 has two enable input pins which are (1 marks)

and

1. ENP, ENT (Page 285)
2. ENI, ENC
3. ENP, ENC
4. ENT, ENI

Correct answer: ENP, ENT (Page 285)

Q7. is said to occur when multiple internal variables change due to change in one input variable (1 marks)

1. Clock Skew
2. Race condition (Page 267)
3. Hold delay
4. Hold and Wait

Correct answer: Race condition (Page 267)

Q8. The (1 marks)

input overrides the

input

1. Asynchronous, synchronous (Page 369)
2. Synchronous, asynchronous
3. Preset input (PRE), Clear input (CLR)
4. Clear input (CLR), Preset input (PRE)

Correct answer: Asynchronous, synchronous (Page 369)

Q9. A decade counter is (1 marks)

1. Mod-3 counter
2. Mod-5 counter
3. Mod-8 counter
4. Mod-10 counter (Page 274)

Correct answer: Mod-10 counter (Page 274)

Q10. In asynchronous transmission when the transmission line is idle, (1 marks)

1. It is set to logic low
2. It is set to logic high (Page 356)
3. Remains in previous state

Correct answer: It is set to logic high (Page 356)

Q11. A Nibble consists of (1 marks)

bits

1. 2
2. 4 (Page 394)
3. 8
4. 16

Correct answer: 4 (Page 394)

Q12. The output of this circuit is always (1 marks)

1. 1
2. 0

Q13. Excess-8 code assigns (1 marks)

to “-8”

1. 1110
2. 1100
3. 1000
4. 0000 (Page 34)

Correct answer: 0000 (Page 34)

Q14. The voltage gain of the Inverting Amplifier is given by the relation (1 marks)

1. Vout / Vin = - Rf / Ri (Page 446)
2. Vout / Rf = - Vin / Ri
3. Rf / Vin = - Ri / Vout
4. Rf / Vin = Ri / Vout

Correct answer: Vout / Vin = - Rf / Ri (Page 446)

Q15. (1 marks)

1. Look Up Table (Page 439)
2. Local User Terminal
3. Least Upper Time Period
4. None of given options

Correct answer: Look Up Table (Page 439)