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CS302 Final Term Solved Subjective Set 3 by Junaid

Digital Logic Design PDF 753 KBUpdated 23 Oct 2026
Final term past paper CS302 Final Term Solved Subjective Set 3 by Junaid PDF 753 KB
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Final term past paper
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CS302 Digital Logic Design
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23 Oct 2026
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Q1. In the highest frequency component in an analog signal is 20 KHz, what is the minimum sample

frequency (Marks 2)

Answer: In the highest frequency component in an analog signal is 20 KHz, and minimum sample frequency is 40 KHz.

Q2. Write down the ABEL symbols that are used for NOT, AND, OR and XOR operations. (Marks 2)

Answer: Page 201

Logic Operation ABEL Symbol NOT AND OR XOR

Q3. Differentiate between Moore machine and Mealy machine. (Marks 2)

Answer: Page 318 The Sequential circuit whose output depends on the current state and the input is known as Mealy Machine. Sequential circuit whose output is determined by the current state only is known as Moore Machine.

Q4. How many bytes will be there in 16K x 8 memory? (Marks 2)

Answer: Page 395 A 16 K x 8 memory, stores 16K bytes or 16 x 1024 = 16384 bytes or 131072 bits.

Q5. How many address bits are required for a 2048-bit memory organized as a 256 x 8 memory? (Marks 3)

Q6. Explain Rotate Right Operation of shift register with the help of Diagram. (Marks 3)

Answer: Page 354 The serial output of the register is connected to the serial input of the register. By applying clock pulses data is shifted right. The data shifted out of the serial out pin at the right hand side is re-circulated back into the shift register input at the left hand side. Thus the data is rotated right within the register.

Q7. Difference between State Assignment and State Reduction process.

(Marks 3)

Answer: (Page 332 & 335)

  1. In state Reduction A state diagram show the sequence of current and next states through which the state machine sequences while in State Assignment Each state in a sequential circuit is identified by a unique combination of binary bits.
  2. In state Reduction the transition from a current state to the next state is determined by current state and the inputs while in State Assignment the states can be selected to allow minimum bit changes when changing from one state to the other.
  3. State Assignment results in simpler combinational circuits that determine the next state while Reduction in the number of state results in fewer flip-flops and a simpler circuit.

Q8. Explain Full-Adder Sum and Carry out Boolean Expression.

(Marks 3)

Answer: (Page 135)

Full-Adder Sum & Carry Out Boolean Expressions

The Sum and Carry Out expressions of the Full-Adder can be determined from the function table. The Full-Adder Sum and Carry Out outputs are defined by the expressions Sum = ABC + ABC + ABC + ABC Sum = A(BC + BC) + A(BC + BC) Sum = A(B ⊕ C) + A(B ⊕ C) Sum = A ⊕ B ⊕ C

CarryOut = ABC + ABC + ABC + ABC CarryOut = C(AB + AB) + AB(C + C) CarryOut = C(A ⊕ B) + AB

Q9. Explain Latches in your own words.(Marks 5)

Answer: (Page 218) A latch is a temporary storage device that has two stable states. A latch output can change from one state to the other by applying appropriate inputs. A latch normally has two inputs, the binary input combinations at the latch input allows the latch to change its state. A latch has two outputs Q and its complement Q(bar). The latch is said to be in logic high state when Q=1 and Q(bar)=0 and it is in the logic low state when Q=0 and Q(bar)=1. When the latch is set to a certain state it retains its state unless the inputs are changed to set the latch to a new state. Thus a latch is a memory element which is able to retain the information stored in it.

Q10. Differentiate between synchronous and asynchronous memory.

(Marks 5)

Answer: (Page 406) In the Asynchronous memory the various input signals are asynchronous and are not tied to the clock, whereas in the Synchronous memory all the inputs are synchronized with respect to the clock and are latched into their various registers on an active clock pulse edge.

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