CS302 Final Term Quiz 4 MCQs by A&I

Cs302 · Digital Logic Design · Final Term Most Important & Repeated MCQs · Final Term Preparation 2022 · ❖ Midterm Short Notes · ❖ Final Term Short Notes · ❖ Mid Term Past Paper · ❖ Final Term Past Paper · ❖ Mega File · ❖ Important Question · ❖ Repeated Question · ❖ Solved Past Paper · ❖ Moaz & Waqar · ❖ Accurate Assignment ❖ Quiz File · ❖ Accurate GDB ❖ Current Paper ❖ Vu New Update · DE multiplexer converts _______ data to __________ data

❖ Parallel data, serial data ❖ Serial data, parallel data (Page 356) ❖ Encoded data, decoded data ❖ All of the given options.

If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop

❖ 0 ❖ 1 (Page 230) ❖ Invalid ❖ Input is invalid

If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop

❖ 0 ❖ 1 ❖ Invalid (Page 230) ❖ Input is invalid In asynchronous digital systems all the circuits change their state with respect to a common clock

❖ True ❖ False (Page 245)

A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is

❖ 10 mW ❖ 25 mW (Page 242) ❖ 64 mW ❖ 1024

A divide-by-50 counter divides the input ______ signal to a 1 Hz signal.

❖ 10 Hz ❖ 50 Hz (Page 298) ❖ 100 Hz ❖ 500 Hz