CS302 Final Term Solved MCQs with References Set 2 by Eagle Eye

Spring 2010

CS302Digital Logic Design

Time: 90 min Marks: 58

Q1. A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register. (1 marks)

1. 1
2. 2
3. 4
4. 8

Q2. A frequency counter ______________ (1 marks)

1. Counts pulse width
2. Counts no. of clock pulses in 1 second
3. Counts high and low range of given clock pulse
4. None of given options

Q3. In a sequential circuit the next state is determined by ________ and _______ (1 marks)

1. State variable, current state
2. Current state, flip-flop output
3. Current state and external input
4. Input and clock signal applied

Q4. The divide-by-60 counter in digital clock is implemented by using two cascading counters: (1 marks)

1. Mod-6, Mod-10
2. Mod-50, Mod-10
3. Mod-10, Mod-50
4. Mod-50, Mod-6

Q5. In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained. (1 marks)

1. True
2. False

Q6. Flip flops are also called _____________ (1 marks)

1. Bi-stable dualvibrators
2. Bi-stable transformer
3. Bi-stable multivibrators
4. Bi-stable singlevibrators

Q7. The minimum time for which the input signal has to be maintained at the input of flip- (1 marks)

flop is called ______ of the flip-flop.

1. Set-up time
2. Hold time
3. Pulse Interval time
4. Pulse Stability time (PST)

Q8. 74HC163 has two enable input pins which are _______ and _________ (1 marks)

1. ENP, ENT
2. ENI, ENC
3. ENP, ENC
4. ENT, ENI

Q9. ____________ is said to occur when multiple internal variables change due to change in one input variable (1 marks)

1. Clock Skew
2. Race condition
3. Hold delay
4. Hold and Wait

Q10. Given the state diagram of an up/down counter, we can find ________ (1 marks)

1. The next state of a given present state
2. The previous state of a given present state
3. Both the next and previous states of a given state
4. The state diagram shows only the inputs/outputs of a given states

Q11. (1 marks)

1. Asynchronous, synchronous
2. Synchronous, asynchronous
3. Preset input (PRE), Clear input (CLR)
4. Clear input (CLR), Preset input (PRE)

Q12. A logic circuit with an output (1 marks)

consists of ________.

1. two AND gates, two OR gates, two inverters
2. three AND gates, two OR gates, one inverter
3. two AND gates, one OR gate, two inverters
4. two AND gates, one OR gate

Q13. A decade counter is __________. (1 marks)

1. Mod-3 counter
2. Mod-5 counter
3. Mod-8 counter
4. Mod-10 counter

Q14. In asynchronous transmission when the transmission line is idle, _________ (1 marks)

1. It is set to logic low
2. It is set to logic high
3. Remains in previous state
4. State of transmission line is not used to start transmission

Q15. A Nibble consists of _____ bits (1 marks)

1. 2
2. 4
3. 8
4. 16

Q16. The output of this circuit is always ________. (1 marks)

1. 1
2. 0
3. A

Q17. Excess-8 code assigns _______ to “-8” (1 marks)

1. 1110
2. 1100
3. 1000
4. 0000

Q18. The voltage gain of the Inverting Amplifier is given by the relation ________ (1 marks)

1. Vout / Vin = - Rf / Ri
2. Vout / Rf = - Vin / Ri
3. Rf / Vin = - Ri / Vout
4. Rf / Vin = Ri / Vout

Q19. LUT is acronym for ________ (1 marks)

1. Look Up Table
2. Local User Terminal
3. Least Upper Time Period
4. None of given options

Q20. DRAM stands for __________ (1 marks)

1. Dynamic RAM
2. Data RAM
3. Demoduler RAM
4. None of given options